[S] Change in coreboot[master]: mb/google/brya/var/agah: Update NVVDD VR PGOOD GPP_E3

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67288 )

Change subject: mb/google/brya/var/agah: Update NVVDD VR PGOOD GPP_E3
......................................................................

mb/google/brya/var/agah: Update NVVDD VR PGOOD GPP_E3

This pin was originally set as output in error.  This should be
a input to behave like GPP_E16 on the older variants.

BUG=b:239721380
TEST=build

Signed-off-by: Tarun Tuli 
Change-Id: Ic0f793ff52adb425ae5378b88d2837bb9e58edd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67288
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: Paul Menzel 
---
M src/mainboard/google/brya/variants/agah/variant.c
1 file changed, 21 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/agah/variant.c b/src/mainboard/google/brya/variants/agah/variant.c
index 9512522..247913e 100644
--- a/src/mainboard/google/brya/variants/agah/variant.c
+++ b/src/mainboard/google/brya/variants/agah/variant.c
@@ -155,7 +155,7 @@
    	gpu_off_seq[3].pwr_en_gpio = GPP_E10;
    } else {
    	const struct pad_config board_rev_3_gpios[] = {
-			PAD_CFG_GPO(GPP_E3, 0, PLTRST),
+			PAD_CFG_GPI(GPP_E3, NONE, PLTRST),
    		PAD_NC(GPP_E10, NONE),
    		PAD_NC(GPP_E16, NONE),
    		PAD_CFG_GPO(GPP_F12, 0, PLTRST),