Name of user not set #1005283 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79979?usp=email )
Change subject: mainboard: Add MSI MS-7707 ......................................................................
mainboard: Add MSI MS-7707
NOTES: * This is the product of a beginner running `autoport` please forgive any gaps in my knowledge about the project * There are still some ugly hacks in this commit that I would like to test and eventually fix * I still probably need to properly fill in documentation * I also probably should understand everything in this commit! (not just let autoport to the heavy lifting) * And I need to look over the `FIXME`s
* MSI h61m-p31/w8 * Winbond 25Q64FVSIG * Fintek F71868AD
Working: * PCIe graphics * Integrated graphics * USB (all ports) * Ethernet
Yet-to-be-thoroughly-tested: * All SATA ports * All PCIe ports (as in the x1 lane) * Super/IO (is my chip supported?) * Suspend states * Integrated graphics (libgfxinit) * ME (and neutering it?)
Untested: * PS/2
Change-Id: Ia7830fcc7552e9734ec7c57e508a6a77f689e5b0 --- M src/device/device.c A src/mainboard/msi/ms7788/Kconfig A src/mainboard/msi/ms7788/Kconfig.name A src/mainboard/msi/ms7788/Makefile.inc A src/mainboard/msi/ms7788/acpi/ec.asl A src/mainboard/msi/ms7788/acpi/platform.asl A src/mainboard/msi/ms7788/acpi/superio.asl A src/mainboard/msi/ms7788/acpi_tables.c A src/mainboard/msi/ms7788/board_info.txt A src/mainboard/msi/ms7788/devicetree.cb A src/mainboard/msi/ms7788/dsdt.asl A src/mainboard/msi/ms7788/early_init.c A src/mainboard/msi/ms7788/gma-mainboard.ads A src/mainboard/msi/ms7788/gpio.c A src/mainboard/msi/ms7788/hda_verb.c A src/mainboard/msi/ms7788/mainboard.c M src/northbridge/intel/sandybridge/romstage.c 17 files changed, 467 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79979/1
diff --git a/src/device/device.c b/src/device/device.c index a635e73..c3d08c4 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -595,6 +595,7 @@ } }
+/* static void final_link(struct bus *link) { struct device *dev; @@ -608,6 +609,7 @@ final_link(c_link); } } +*/ /** * Finalize all devices in the global device tree. * @@ -616,16 +618,19 @@ */ void dev_finalize(void) { - struct bus *link; + //struct bus *link;
printk(BIOS_INFO, "Finalize devices...\n");
/* First call the mainboard finalize. */ final_dev(&dev_root);
+ // HACK: the boot hangs here, so I'm getting rid of it + // it's probably important but everything works so :shrug: + /* Now finalize everything. */ - for (link = dev_root.link_list; link; link = link->next) - final_link(link); + //for (link = dev_root.link_list; link; link = link->next) + // final_link(link);
printk(BIOS_INFO, "Devices finalized\n"); } diff --git a/src/mainboard/msi/ms7788/Kconfig b/src/mainboard/msi/ms7788/Kconfig new file mode 100644 index 0000000..284966a --- /dev/null +++ b/src/mainboard/msi/ms7788/Kconfig @@ -0,0 +1,32 @@ +if BOARD_MSI_MS_7788 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + # maybe wrong + select MAINBOARD_HAS_LIBGFXINIT + #select SUPERIO_FINTEK_F71869AD + +config MAINBOARD_DIR + string + default "msi/ms_7788" + +config MAINBOARD_PART_NUMBER + string + default "MS-7788" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/msi/ms7788/Kconfig.name b/src/mainboard/msi/ms7788/Kconfig.name new file mode 100644 index 0000000..db061b2 --- /dev/null +++ b/src/mainboard/msi/ms7788/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_MS_7788 + bool "MS-7788" diff --git a/src/mainboard/msi/ms7788/Makefile.inc b/src/mainboard/msi/ms7788/Makefile.inc new file mode 100644 index 0000000..18391d8 --- /dev/null +++ b/src/mainboard/msi/ms7788/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/msi/ms7788/acpi/ec.asl b/src/mainboard/msi/ms7788/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/ms7788/acpi/ec.asl diff --git a/src/mainboard/msi/ms7788/acpi/platform.asl b/src/mainboard/msi/ms7788/acpi/platform.asl new file mode 100644 index 0000000..afb8abb --- /dev/null +++ b/src/mainboard/msi/ms7788/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/msi/ms7788/acpi/superio.asl b/src/mainboard/msi/ms7788/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/ms7788/acpi/superio.asl diff --git a/src/mainboard/msi/ms7788/acpi_tables.c b/src/mainboard/msi/ms7788/acpi_tables.c new file mode 100644 index 0000000..e275965 --- /dev/null +++ b/src/mainboard/msi/ms7788/acpi_tables.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi_gnvs.h> +#include <soc/nvs.h> + +/* FIXME: check this function. */ +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* The lid is open by default. */ + gnvs->lids = 1; + + /* Temperature at which OS will shutdown */ + gnvs->tcrt = 100; + /* Temperature at which OS will throttle CPU */ + gnvs->tpsv = 90; +} diff --git a/src/mainboard/msi/ms7788/board_info.txt b/src/mainboard/msi/ms7788/board_info.txt new file mode 100644 index 0000000..517c3d3 --- /dev/null +++ b/src/mainboard/msi/ms7788/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM protocol: SPI +Flashrom support: 7 +ROM package: SOIC-8 +ROM socketed: n +FIXME: check category, , put ROM package, ROM socketed, Release year diff --git a/src/mainboard/msi/ms7788/devicetree.cb b/src/mainboard/msi/ms7788/devicetree.cb new file mode 100644 index 0000000..6757677 --- /dev/null +++ b/src/mainboard/msi/ms7788/devicetree.cb @@ -0,0 +1,73 @@ +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply. + register "spd_addresses" = "{0x50, 0, 0x52, 0}" + device domain 0x0 on + subsystemid 0x1462 0x7788 inherit + + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x00fc0291" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device ref mei1 on # Management Engine Interface 1 + end + device ref mei2 off # Management Engine Interface 2 + end + device ref me_ide_r off # Management Engine IDE-R + end + device ref me_kt off # Management Engine KT + end + device ref gbe off # Intel Gigabit Ethernet + end + device ref ehci2 on # USB2 EHCI #2 + end + device ref hda on # High Definition Audio + end + device ref pcie_rp1 on # PCIe Port #1 + end + device ref pcie_rp2 off # PCIe Port #2 + end + device ref pcie_rp3 off # PCIe Port #3 + end + device ref pcie_rp4 off # PCIe Port #4 + end + device ref pcie_rp5 on # PCIe Port #5 + end + device ref pcie_rp6 off # PCIe Port #6 + end + device ref pcie_rp7 off # PCIe Port #7 + end + device ref pcie_rp8 off # PCIe Port #8 + end + device ref ehci1 on # USB2 EHCI #1 + end + device ref pci_bridge off # PCI bridge + end + device ref lpc on # LPC bridge + end + device ref sata1 on # SATA Controller 1 + end + device ref smbus on # SMBus + end + device ref sata2 off # SATA Controller 2 Unsupported PCI device 8086:1c08 + end + device ref thermal off # Thermal + end + end + device ref host_bridge on # Host bridge Host bridge + subsystemid 0x1462 0x7788 + end + device ref peg10 on # PEG + subsystemid 0x1462 0x7788 + end + device ref igd on # iGPU + end + end +end diff --git a/src/mainboard/msi/ms7788/dsdt.asl b/src/mainboard/msi/ms7788/dsdt.asl new file mode 100644 index 0000000..7d13c55 --- /dev/null +++ b/src/mainboard/msi/ms7788/dsdt.asl @@ -0,0 +1,30 @@ +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/msi/ms7788/early_init.c b/src/mainboard/msi/ms7788/early_init.c new file mode 100644 index 0000000..0b4c0fb --- /dev/null +++ b/src/mainboard/msi/ms7788/early_init.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <bootblock_common.h> +#include <device/pci_ops.h> +#include <southbridge/intel/bd82x6x/pch.h> + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +/* +void bootblock_mainboard_early_init(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x370f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} +*/ diff --git a/src/mainboard/msi/ms7788/gma-mainboard.ads b/src/mainboard/msi/ms7788/gma-mainboard.ads new file mode 100644 index 0000000..c6087ba --- /dev/null +++ b/src/mainboard/msi/ms7788/gma-mainboard.ads @@ -0,0 +1,22 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (LVDS, + eDP, + DP1, + DP2, + DP3, + HDMI1, -- also DVI-D, or HDMI over DP++ + HDMI2, + HDMI3, + Analog); -- legacy VGA port, or analog part of DVI-I (HDMI1, -- DVI-D connector + +end GMA.Mainboard; diff --git a/src/mainboard/msi/ms7788/gpio.c b/src/mainboard/msi/ms7788/gpio.c new file mode 100644 index 0000000..f3e4bad --- /dev/null +++ b/src/mainboard/msi/ms7788/gpio.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/msi/ms7788/hda_verb.c b/src/mainboard/msi/ms7788/hda_verb.c new file mode 100644 index 0000000..b77173d --- /dev/null +++ b/src/mainboard/msi/ms7788/hda_verb.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1462d788, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x1462d788), + AZALIA_PIN_CFG(0, 0x11, 0x411111f0), + AZALIA_PIN_CFG(0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0, 0x14, 0x01014410), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19c30), + AZALIA_PIN_CFG(0, 0x19, 0x02a19c40), + AZALIA_PIN_CFG(0, 0x1a, 0x0181343f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x4005c603), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1f, 0x411111f0), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/ms7788/mainboard.c b/src/mainboard/msi/ms7788/mainboard.c new file mode 100644 index 0000000..3171d65 --- /dev/null +++ b/src/mainboard/msi/ms7788/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + + +static void mainboard_enable(struct device *dev) +{ + // FIXME + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 56dc677..79ec484 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -50,8 +50,14 @@ { int s3resume = 0;
- if (mchbar_read16(SSKPD_HI) == 0xcafe) - system_reset(); + // HACK: I have no clue what is going on here, but the boot hangs + // so I'm just removing the check + printk(BIOS_DEBUG, "checking system reset\n"); + + //if (mchbar_read16(SSKPD_HI) == 0xcafe) + //system_reset(); + + printk(BIOS_DEBUG, "system didn't reset!\n");
/* Init LPC, GPIO, BARs, disable watchdog ... */ early_pch_init();