Change in coreboot[master]: soc/intel/alderlake: Enable TME for Alder Lake

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

soc/intel/alderlake: Enable TME for Alder Lake

List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.

TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.

Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46296/1

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 3f500f3..2d21a61 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -25,6 +25,7 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select IOAPIC
+	select INTEL_TME
    select MRC_SETTINGS_PROTECT
    select PARALLEL_MP
    select PARALLEL_MP_AP_WORK
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 80420f0..b96222c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -155,6 +155,9 @@
    /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
    dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
    m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev);
+
+	/* Change TmeEnable UPD value according to INTEL_TME Kconfig */
+	m_cfg->TmeEnable = CONFIG(INTEL_TME);
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

Patch Set 1: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/46296/1/src/soc/intel/alderlake/rom... 
File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/46296/1/src/soc/intel/alderlake/rom... 
PS1, Line 159: /* Change TmeEnable UPD value according to INTEL_TME Kconfig */
I think this comment is a biiit redundant, we might as well drop it

(same applies to other comments, but can be done in another patch)

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46296

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

soc/intel/alderlake: Enable TME for Alder Lake

List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.

TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.

Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/46296/2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46296/1/src/soc/intel/alderlake/rom... 
File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/46296/1/src/soc/intel/alderlake/rom... 
PS1, Line 159: /* Change TmeEnable UPD value according to INTEL_TME Kconfig */
> I think this comment is a biiit redundant, we might as well drop it […]

Ack

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

Patch Set 2: Code-Review+2

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

Patch Set 2: Code-Review+2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

Patch Set 2: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46296 )

Change subject: soc/intel/alderlake: Enable TME for Alder Lake
......................................................................

soc/intel/alderlake: Enable TME for Alder Lake

List of changes:
1. Select CONFIG_INTEL_TME from SoC Kconfig
2. Set TmeEnable FSP-M UPD based on Kconfig.

TEST=Able to build and boot ADLRVP and verified from Chrome OS
that TME is enable.

Change-Id: I6992957bd2999a2efbae7b6d9c825c43bd118f72
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46296
Reviewed-by: Angel Pons 
Reviewed-by: V Sowmya 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  V Sowmya: Looks good to me, approved
  Angel Pons: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 3f500f3..2d21a61 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -25,6 +25,7 @@
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select IOAPIC
+	select INTEL_TME
    select MRC_SETTINGS_PROTECT
    select PARALLEL_MP
    select PARALLEL_MP_AP_WORK
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 80420f0..38c1a1b 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -155,6 +155,8 @@
    /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
    dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
    m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev);
+
+	m_cfg->TmeEnable = CONFIG(INTEL_TME);
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)