Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46756 )
Change subject: nb/intel/haswell: Place CTDP ASL code in a separate scope ......................................................................
nb/intel/haswell: Place CTDP ASL code in a separate scope
This is just to align the code with what Broadwell does.
Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl 2 files changed, 6 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46756/1
diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 7e59fb5..84c0f2f 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-//Scope (_SB.PCI0.MCHC) -//{ +Scope (_SB.PCI0.MCHC) +{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -219,4 +219,4 @@ Release (CTCM) Return (1) } -//} +} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index ad38f4d..08f4471 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -80,8 +80,6 @@ Offset (0xbc), // Top of Low Used Memory TLUD, 32, } - - #include "ctdp.asl" }
// Current Resource Settings @@ -227,3 +225,6 @@
Return (MCRS) } + +/* Configurable TDP */ +#include "ctdp.asl"
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46756
to look at the new patch set (#2).
Change subject: nb/intel/haswell: Place CTDP ASL code in a separate scope ......................................................................
nb/intel/haswell: Place CTDP ASL code in a separate scope
This is just to align the code with what Broadwell does.
Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl 2 files changed, 6 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46756/2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46756 )
Change subject: nb/intel/haswell: Place CTDP ASL code in a separate scope ......................................................................
Patch Set 9: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46756 )
Change subject: nb/intel/haswell: Place CTDP ASL code in a separate scope ......................................................................
nb/intel/haswell: Place CTDP ASL code in a separate scope
This is just to align the code with what Broadwell does.
Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46756 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl 2 files changed, 6 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 7e59fb5..84c0f2f 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-//Scope (_SB.PCI0.MCHC) -//{ +Scope (_SB.PCI0.MCHC) +{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -219,4 +219,4 @@ Release (CTCM) Return (1) } -//} +} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index f36895d..dc3a36f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -80,8 +80,6 @@ Offset (0xbc), // Top of Low Used Memory TLUD, 32, } - - #include "ctdp.asl" }
// Current Resource Settings @@ -227,3 +225,6 @@
Return (MCRS) } + +/* Configurable TDP */ +#include "ctdp.asl"
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)