[S] Change in coreboot[main]: [UNTESTED] soc/amd/genoa: add CPPU support

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79528?usp=email )

Change subject: [UNTESTED] soc/amd/genoa: add CPPU support
......................................................................

[UNTESTED] soc/amd/genoa: add CPPU support

Select SOC_AMD_COMMON_BLOCK_ACPI_CPPC to add the common AMD CPPC code
that writes the CPPC information in the CPU devices in the SSDT and
implement the functionality to get the minimum and nominal frequencies
from the SMU. The SMU message IDs for this have been taken from the
SMC_MSG typedef in openSIL code.

Signed-off-by: Felix Held 
Change-Id: Icc40a92810e845dc8eeba3908f5bfce274df2ab9
---
M src/soc/amd/genoa/Kconfig
M src/soc/amd/genoa/Makefile.inc
A src/soc/amd/genoa/cppc.c
M src/soc/amd/genoa/include/soc/smu.h
4 files changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/79528/1

diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 592043e..29d9c0d 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -14,6 +14,7 @@
    select SOC_AMD_COMMON
    select SOC_AMD_COMMON_BLOCK_ACPI
    select SOC_AMD_COMMON_BLOCK_ACPIMMIO
+	select SOC_AMD_COMMON_BLOCK_ACPI_CPPC
    select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
    select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
    select SOC_AMD_COMMON_BLOCK_AOAC
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index 30efcaf..bb94c80 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -16,6 +16,7 @@
 ramstage-y	+= acpi.c
 ramstage-y	+= aoac.c
 ramstage-y	+= chip.c
+ramstage-y	+= cppc.c
 ramstage-y	+= cpu.c
 ramstage-y	+= domain.c
 ramstage-y	+= fch.c
diff --git a/src/soc/amd/genoa/cppc.c b/src/soc/amd/genoa/cppc.c
new file mode 100644
index 0000000..2fee2a0
--- /dev/null
+++ b/src/soc/amd/genoa/cppc.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/cppc.h>
+#include <amdblocks/smu.h>
+#include <console/console.h>
+#include <soc/smu.h>
+#include <types.h>
+
+static enum cb_err smu_cppc_query(enum smu_message_id smu_msg_id, uint32_t *freq)
+{
+	struct smu_payload smu_payload = {0};
+
+	if (send_smu_message(smu_msg_id, &smu_payload) != CB_SUCCESS)
+		return CB_ERR;
+
+	*freq = smu_payload.msg[0];
+	return CB_SUCCESS;
+}
+
+enum cb_err get_ccx_cppc_min_frequency(uint32_t *freq)
+{
+	static uint32_t min_freq;
+
+	if (!min_freq)
+		if (smu_cppc_query(SMC_MSG_GetCPPCLowestFrequency, &min_freq) != CB_SUCCESS)
+			return CB_ERR;
+
+	*freq = min_freq;
+	printk(BIOS_SPEW, "CCX CPPC min speed: %d MHz\n", *freq);
+	return CB_SUCCESS;
+}
+
+enum cb_err get_ccx_cppc_nom_frequency(uint32_t *freq)
+{
+	static uint32_t nom_freq;
+
+	if (!nom_freq)
+		if (smu_cppc_query(SMC_MSG_GetCPPCNominalFrequency, &nom_freq) != CB_SUCCESS)
+			return CB_ERR;
+
+	*freq = nom_freq;
+	printk(BIOS_SPEW, "CCX CPPC nom speed: %d MHz\n", *freq);
+
+	return CB_SUCCESS;
+}
diff --git a/src/soc/amd/genoa/include/soc/smu.h b/src/soc/amd/genoa/include/soc/smu.h
index 6ab0c06..ab62411 100644
--- a/src/soc/amd/genoa/include/soc/smu.h
+++ b/src/soc/amd/genoa/include/soc/smu.h
@@ -12,6 +12,8 @@

enum smu_message_id {
    SMC_MSG_S3ENTRY = 0x0b,
+	SMC_MSG_GetCPPCNominalFrequency = 0x39,
+	SMC_MSG_GetCPPCLowestFrequency = 0x3a,
 };

/*