Change in ...coreboot[master]: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31291
Change subject: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand ......................................................................
cpu/intel/car/*/cache_as_ram.S: Add brackets around operand
Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/31291/1
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index f32b3dc..7788a2d 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -118,7 +118,7 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax wrmsr
movl $MTRR_PHYS_MASK(1), %ecx diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index f84e855..9d50582 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -304,7 +304,7 @@ /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31291 )
Change subject: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31291 )
Change subject: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand ......................................................................
Patch Set 1: Code-Review+1
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31291 )
Change subject: cpu/intel/car/*/cache_as_ram.S: Add brackets around operand ......................................................................
cpu/intel/car/*/cache_as_ram.S: Add brackets around operand
Change-Id: I644c38c9b8383db25a970dc7a5ec8765980298ed Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/31291 Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve HAOUAS Elyes: Looks good to me, approved
diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index f32b3dc..7788a2d 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -118,7 +118,7 @@ /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax wrmsr
movl $MTRR_PHYS_MASK(1), %ecx diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index f84e855..9d50582 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -304,7 +304,7 @@ /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
-
Arthur Heymans (Code Review) -
HAOUAS Elyes (Code Review)
-
Kyösti Mälkki (Code Review)
-
Paul Menzel (Code Review)