Patch set updated for coreboot: 6f62ed2 lenovo/x60/i915.c: Place GTT below top of memory

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5927

-gerrit

commit 6f62ed2ec04386fcdd1aacde89649c8baf312d8e
Author: Paul Menzel 
Date:   Thu Jun 5 22:45:35 2014 +0200

lenovo/x60/i915.c: Place GTT below top of memory

Since commit 17fec8a0 [1]

drm/i915: Use Graphics Base of Stolen Memory on all gen3+

present in the Linux kernel since version 3.12, 3D does not work
    anymore [2].

Comparing the graphics registers, in this case that means output of
    `intel_reg_dumper`, the vendor Video BIOS is setting the register
    PGTBL_CTL/PGETBL_CTL, only document in the i965 datasheet [3], to
    `0x3ffc0001`, while it is set to `0x3f800001` by the native graphics
    init code.

Currently native graphis init sets the GTT right above the base
    address of stolen memory. The Video BIOS sets it below top of memory.
    The Linux Intel driver expects it to be below top of memory, so do it
    this way, by setting the address to TOM minus the size of the GTT,
    which is hardcoded to 256 KiB.

There is still an error PTE error reported during boot, but 3D works
    with Linux 3.12+ and no user visible problems are shown.

Currently there are the two defines `PGETBL_CTL` and `PGETLB_CTL`.
    Use the one using TBL as the abbreviation for *table* and which is
    the name used in the Intel 965 datasheet.

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=1...
    [2] https://bugs.freedesktop.org/show_bug.cgi?id=79038
    [3] https://01.org/linuxgraphics/sites/default/files/documentation/965_g35_vol_1...
        Intel ® 965 Express Chipset Family and
          Intel ® G35 Express Chipset Graphics Controller
          Programmer’s Reference Manual
        Volume 1: Graphics Core
        Revision 1.0a

Change-Id: I0a5b04c2c5300f5056cb48075aa5804984bc9948
    Signed-off-by: Paul Menzel 
---
 src/mainboard/lenovo/x60/i915.c     | 11 ++++++++++-
 src/mainboard/lenovo/x60/i915_reg.h |  2 ++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/lenovo/x60/i915.c b/src/mainboard/lenovo/x60/i915.c
index 8fbd2a1..be5199e 100644
--- a/src/mainboard/lenovo/x60/i915.c
+++ b/src/mainboard/lenovo/x60/i915.c
@@ -134,11 +134,20 @@ int gtt_setup(unsigned int mmiobase);
 int gtt_setup(unsigned int mmiobase)
 {
    unsigned long PGETBL_save;
+	unsigned long tom;

PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
    PGETBL_save |= PGETBL_ENABLED;

-	PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
+	/* The Video BIOS places the GTT right below top of memory.
+	 * It is not documented in the Intel 945 datasheet, but the Intel
+	 * developers said that it is normally placed there.
+	 *
+	 * TODO: Add option table value to make the GTT size runtime
+	 * configurable.
+	 */
+	tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24;
+	pgetbl_ctl |= tom - 256 * KiB;
    PGETBL_save |= 2; /* set GTT to 256kb */

write32(mmiobase + GFX_FLSH_CNTL, 0);
diff --git a/src/mainboard/lenovo/x60/i915_reg.h b/src/mainboard/lenovo/x60/i915_reg.h
index 382b822..a12ba55 100644
--- a/src/mainboard/lenovo/x60/i915_reg.h
+++ b/src/mainboard/lenovo/x60/i915_reg.h
@@ -27,6 +27,8 @@

#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))

+#define TOLUD 0x9c
+
 /*
  * The Bridge device's PCI config space has information about the
  * fb aperture size and the amount of pre-reserved memory.