Change in coreboot[master]: soc/intel/skx: Lets iasl automatically resolve _PRT package size
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/skx: Lets iasl automatically resolve _PRT package size ......................................................................
soc/intel/skx: Lets iasl automatically resolve _PRT package size
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries.
Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 1 file changed, 98 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41529/1
diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index 2f5328f..9926367 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -7,225 +7,225 @@ */
#define GEN_PCIE_LEGACY_IRQ() \ - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 } + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }
#define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ - Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ - Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ - Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + Package () { ##dev, 0x00, LNKA, 0x00 }, \ + Package () { ##dev, 0x01, LNKB, 0x00 }, \ + Package () { ##dev, 0x02, LNKC, 0x00 }, \ + Package () { ##dev, 0x03, LNKD, 0x00 }
#define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq } + Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0003FFFF, 0x00, 0x00, ##irq }
#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ - Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ - Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ - Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + Package () { ##dev, 0x00, 0x00, ##irq1 }, \ + Package () { ##dev, 0x01, 0x00, ##irq2 }, \ + Package () { ##dev, 0x02, 0x00, ##irq3 }, \ + Package () { ##dev, 0x03, 0x00, ##irq4 }
// Socket 0, IIOStack 0 device legacy interrupt routing Name (PR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, // [CB0A]: CBDMA // [CB0E]: CBDMA - Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, // [CB0B]: CBDMA // [CB0F]: CBDMA - Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, // [CB0C]: CBDMA // [CB0G]: CBDMA - Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, // [CB0D]: CBDMA // [CB0H]: CBDMA - Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, // Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, // // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, })
// Socket 0, IIOStack 0 device IOAPIC interrupt routing Name (AR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, // [CB0A]: CB3DMA // [CB0E]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, // [CB0B]: CB3DMA // [CB0F]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, // [CB0C]: CB3DMA // [CB0G]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, // [CB0D]: CB3DMA // [CB0H]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, // [UBX0]: Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, })
// Socket 0, IIOStack 1 device legacy interrupt routing @@ -406,7 +406,7 @@ Name (PR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
// CBDMA GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), @@ -419,7 +419,7 @@ Name (AR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x4F },
// CBDMA GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B),
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/skx: Lets iasl automatically resolve _PRT package size ......................................................................
Patch Set 1: Code-Review+1
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/skx: Lets iasl automatically resolve _PRT package size ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/skx: Lets iasl automatically resolve _PRT package size Please specify soc/intel/xeon_sp/skx instead, since SKX-SP is different from SKX-D (as supported in soc/intel/skylake).
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/skx: Lets iasl automatically resolve _PRT package size ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG@7 PS1, Line 7: Lets no "s": Let
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/skx: Lets iasl automatically resolve _PRT package size ......................................................................
Patch Set 1: Code-Review+1
Hello Lance Zhao, build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Maxim Polyakov, Johnny Lin, Paul Menzel, David Hendricks, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41529
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp/skx: Lets iasl automatically resolve _PRT package size ......................................................................
soc/intel/xeon_sp/skx: Lets iasl automatically resolve _PRT package size
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries.
Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 1 file changed, 98 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41529/2
Hello Lance Zhao, build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Maxim Polyakov, Johnny Lin, Paul Menzel, David Hendricks, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41529
to look at the new patch set (#3).
Change subject: soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size ......................................................................
soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries.
Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 1 file changed, 98 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/41529/3
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG@7 PS1, Line 7: Lets
no "s": Let
Done
https://review.coreboot.org/c/coreboot/+/41529/1//COMMIT_MSG@7 PS1, Line 7: soc/intel/skx: Lets iasl automatically resolve _PRT package size
Please specify soc/intel/xeon_sp/skx instead, since SKX-SP is different from SKX-D (as supported in […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size ......................................................................
soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size
BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries.
Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/41529 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net --- M src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl 1 file changed, 98 insertions(+), 98 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Maxim Polyakov: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index 2f5328f..9926367 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -7,225 +7,225 @@ */
#define GEN_PCIE_LEGACY_IRQ() \ - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 } + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0003FFFF, 0x00, LNKA, 0x00 }
#define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ - Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ - Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ - Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + Package () { ##dev, 0x00, LNKA, 0x00 }, \ + Package () { ##dev, 0x01, LNKB, 0x00 }, \ + Package () { ##dev, 0x02, LNKC, 0x00 }, \ + Package () { ##dev, 0x03, LNKD, 0x00 }
#define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq } + Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0003FFFF, 0x00, 0x00, ##irq }
#define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ - Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ - Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ - Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + Package () { ##dev, 0x00, 0x00, ##irq1 }, \ + Package () { ##dev, 0x01, 0x00, ##irq2 }, \ + Package () { ##dev, 0x02, 0x00, ##irq3 }, \ + Package () { ##dev, 0x03, 0x00, ##irq4 }
// Socket 0, IIOStack 0 device legacy interrupt routing Name (PR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, // [CB0A]: CBDMA // [CB0E]: CBDMA - Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, // [CB0B]: CBDMA // [CB0F]: CBDMA - Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, // [CB0C]: CBDMA // [CB0G]: CBDMA - Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, // [CB0D]: CBDMA // [CB0H]: CBDMA - Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, // Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, // // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, })
// Socket 0, IIOStack 0 device IOAPIC interrupt routing Name (AR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, // [CB0A]: CB3DMA // [CB0E]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, // [CB0B]: CB3DMA // [CB0F]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, // [CB0C]: CB3DMA // [CB0G]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, // [CB0D]: CB3DMA // [CB0H]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, // [UBX0]: Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, })
// Socket 0, IIOStack 1 device legacy interrupt routing @@ -406,7 +406,7 @@ Name (PR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 },
// CBDMA GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), @@ -419,7 +419,7 @@ Name (AR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x4F },
// CBDMA GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B),
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41529 )
Change subject: soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4552 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4551 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4550 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4549
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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Arthur Heymans (Code Review)
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Jonathan Zhang (Code Review)
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Maxim Polyakov (Code Review)
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Patrick Georgi (Code Review)
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Paul Menzel (Code Review)