Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33430
Change subject: grunt: Change Bayhub eMMC clock to 208MHz ......................................................................
grunt: Change Bayhub eMMC clock to 208MHz
The clock was previously set to 52MHz to workaround the fact that depthcharge didn't support tuning.
This patch should only be merged once the following patch lands: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
I'm honestly not sure why forcing the clock to 208MHz is better then telling the part to use SDHC registers to set the clock.
BUG=b:122244718 TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a Signed-off-by: Raul E Rangel rrangel@chromium.org --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33430/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index d1a3492..72092f5 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -61,12 +61,22 @@ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
- /* Set Bayhub SD base CLK 50MHz: case#1 PCR 0x3E4[22] = 0 */ + /* Set Base clock to 208MHz(PCR 0x304[31:16] = 0x2C28) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2C28 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | BH720_PCR_CSR); bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL); + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_CSR);
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC clock to 208MHz ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/33430/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33430/1//COMMIT_MSG@17 PS1, Line 17: So what happens if tuning fails. Does the 208MHz clock present a problem? Should it get set back to 52MHz in depthcharge?
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC clock to 208MHz ......................................................................
Patch Set 1: Code-Review-1
(1 comment)
I'll rework the patch
https://review.coreboot.org/#/c/33430/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33430/1//COMMIT_MSG@17 PS1, Line 17:
So what happens if tuning fails. […]
You bring up a good point. Currently the way the code is written if tuning fails, the broken screen is shown. We should change depthcharge to fall back to a slower speed. I think this also convinces me that we shouldn't override the SDHC clock setting in coreboot, but instead tell the BH part to respect it. This way depthcharge can change the clock sleep without vendor specific code.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC clock to 208MHz ......................................................................
Patch Set 1: -Code-Review
Remove +2 until the design is decided upon.
Hello Daniel Kurtz, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33430
to look at the new patch set (#2).
Change subject: grunt: Change Bayhub eMMC base clock to 200MHz ......................................................................
grunt: Change Bayhub eMMC base clock to 200MHz
The clock was previously set to 52MHz to workaround the fact that depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
BUG=b:122244718 TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a Signed-off-by: Raul E Rangel rrangel@chromium.org --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 12 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33430/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC base clock to 200MHz ......................................................................
Patch Set 2:
PTAL
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC base clock to 200MHz ......................................................................
Patch Set 2: Code-Review+2
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33430 )
Change subject: grunt: Change Bayhub eMMC base clock to 200MHz ......................................................................
grunt: Change Bayhub eMMC base clock to 200MHz
The clock was previously set to 52MHz to workaround the fact that depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+...
BUG=b:122244718 TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a Signed-off-by: Raul E Rangel rrangel@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 12 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 996e610..95274eb 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -61,12 +61,22 @@ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_EMMC_SETTING);
- /* Set Bayhub SD base CLK 50MHz: case#1 PCR 0x3E4[22] = 0 */ + /* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */ + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_READ | BH720_PCR_DrvStrength_PLL); + bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); + bh720_pcr_data &= 0x0000FFFF; + bh720_pcr_data |= 0x2510 << 16; + write32((void *)(sdbar + BH720_MEM_RW_DATA), bh720_pcr_data); + write32((void *)(sdbar + BH720_MEM_RW_ADR), + BH720_MEM_RW_WRITE | BH720_PCR_DrvStrength_PLL); + + /* Use PLL Base clock PCR 0x3E4[22] = 1 */ write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | BH720_PCR_CSR); bh720_pcr_data = read32((void *)(sdbar + BH720_MEM_RW_DATA)); write32((void *)(sdbar + BH720_MEM_RW_DATA), - bh720_pcr_data & ~BH720_PCR_CSR_EMMC_MODE_SEL); + bh720_pcr_data | BH720_PCR_CSR_EMMC_MODE_SEL); write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | BH720_PCR_CSR);
-
Martin Roth (Code Review) -
Raul Rangel (Code Review)