Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )
Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/rom... PS4, Line 136: fsp_memory_init(s3wake); : pmc_set_disb(); : if (!s3wake) { : if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) : cse_fw_sync();
Is there a dependency on having FSP-M run before this? The HECI interface was initialized just before this on line 133
Yes, from past discussions Intel had mentioned that you cannot run HMRPFO when dram is not initialized. That is the reason this is being done after memory init. I think it would be good to add a comment here.
Is the MRC cache data written back to the SPI ROM before CSE FW Sync.
Yes, with Shelley's recent changes, MRC data gets written to cache right away after training.
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Furquan Shaikh (Code Review)