Hello Weiyi Lu,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46400
to review the following change.
Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ......................................................................
soc/mediatek/mt8192: Initialize audio pll tuner frequency
Add AUDPLL TUNER init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/1
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 11750d2..24cfafd 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -392,6 +392,10 @@ for (i = 0; i < ARRAY_SIZE(rates); i++) pll_set_rate(&plls[rates[i].id], rates[i].rate);
+ /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (i == APMIXED_USBPLL)
Hello build bot (Jenkins), Weiyi Lu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46400
to look at the new patch set (#22).
Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ......................................................................
soc/mediatek/mt8192: Initialize audio pll tuner frequency
Add AUDPLL TUNER init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/22
Hello Hung-Te Lin, build bot (Jenkins), Weiyi Lu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46400
to look at the new patch set (#32).
Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ......................................................................
soc/mediatek/mt8192: Initialize audio pll tuner frequency
Add AUDPLL TUNER init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/32
Hello Hung-Te Lin, build bot (Jenkins), Weiyi Lu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46400
to look at the new patch set (#34).
Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ......................................................................
soc/mediatek/mt8192: Initialize audio pll tuner frequency
Add AUDPLL TUNER init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46400/34
Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46400 )
Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ......................................................................
Patch Set 37: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46400 )
Change subject: soc/mediatek/mt8192: Initialize audio pll tuner frequency ......................................................................
soc/mediatek/mt8192: Initialize audio pll tuner frequency
Add AUDPLL TUNER init code.
TEST=Boots correctly on MT8192EVB.
Signed-off-by: Weiyi Lu weiyi.lu@mediatek.com Change-Id: I1f1b5b55a0a16d42311b16b89b15b31e1aa04670 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46400 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Yu-Ping Wu yupingso@google.com --- M src/soc/mediatek/mt8192/pll.c 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 11750d2..24cfafd 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -392,6 +392,10 @@ for (i = 0; i < ARRAY_SIZE(rates); i++) pll_set_rate(&plls[rates[i].id], rates[i].rate);
+ /* AUDPLL Tuner Frequency Set */ + write32(&mtk_apmixed->apll1_tuner_con0, read32(&mtk_apmixed->apll1_con2) + 1); + write32(&mtk_apmixed->apll2_tuner_con0, read32(&mtk_apmixed->apll2_con2) + 1); + /* xPLL Frequency Enable */ for (i = 0; i < APMIXED_PLL_MAX; i++) { if (i == APMIXED_USBPLL)
-
Hung-Te Lin (Code Review) -
Yidi Lin (Code Review)
-
Yu-Ping Wu (Code Review)