Change in coreboot[master]: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP Sili...

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Attention is currently required from: Nico Huber, Jeremy Soller, Angel Pons.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49104 )

Change subject: soc/intel/cannonlake: Allow setting PCIe subsystem IDs after FSP SiliconInit
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Patch Set 10:

(2 comments)

File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49104/comment/fb65b287_1a92e4c8 
PS10, Line 540: 				uint64_t :4;
space prohibited before that ':' (ctx:WxV)

https://review.coreboot.org/c/coreboot/+/49104/comment/c90b0694_05dc0226 
PS10, Line 542: 				uint64_t :16;
space prohibited before that ':' (ctx:WxV)