Patch set updated for coreboot: c3026d0 cpu/amd/model_10xxx: Add support for early cbmem mainboards/amd/fam10: Initialize cbmem area after raminit - coreboot-gerrit

16 Mar 2015

Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8489
-gerrit
commit c3026d016414e206fced099e80a3b6d930d9d90d
Author: Timothy Pearson tpearson@raptorengineeringinc.com
Date:   Fri Mar 13 13:27:58 2015 -0500
cpu/amd/model_10xxx: Add support for early cbmem
    mainboards/amd/fam10: Initialize cbmem area after raminit
When GFXUMA is enabled, CBMEM is placed at TOM - UMASIZE
    When GFXUMA is disabled, CBMEM is placed at TOM
    This matches the behaviour present before conversion to early
    CBMEM.
The CBMEM location code implicitly assumes TOM does not change
    between romstage and ramstage.  TOM is set by romstage raminit,
    and is never changed by romstage or ramstage afterward.  As
    the CBMEM location is positioned at a specific offset from TOM
    that is known to both romstage and ramstage early CBMEM is safe
    on Fam10h systems.
TEST: Booted ASUS KFSN4-DRE and verified both cbmem timestamp
    tables from romstage and cbmem log tables from ramstage.
Change-Id: Idf9e0245fe91185696ff664b06182c26b376c196
    Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com
---
 src/cpu/amd/model_10xxx/ram_calc.c                   | 11 +++++++++++
 src/mainboard/advansus/a785e-i/romstage.c            |  1 +
 src/mainboard/amd/bimini_fam10/romstage.c            |  1 +
 src/mainboard/amd/mahogany_fam10/romstage.c          |  1 +
 src/mainboard/amd/serengeti_cheetah_fam10/romstage.c |  1 +
 src/mainboard/amd/tilapia_fam10/romstage.c           |  1 +
 src/mainboard/asus/kfsn4-dre/romstage.c              |  1 +
 src/mainboard/asus/m4a78-em/romstage.c               |  1 +
 src/mainboard/asus/m4a785-m/romstage.c               |  1 +
 src/mainboard/asus/m5a88-v/romstage.c                |  1 +
 src/mainboard/avalue/eax-785e/romstage.c             |  1 +
 src/mainboard/gigabyte/ma785gm/romstage.c            |  1 +
 src/mainboard/gigabyte/ma785gmt/romstage.c           |  1 +
 src/mainboard/gigabyte/ma78gm/romstage.c             |  1 +
 src/mainboard/hp/dl165_g6_fam10/romstage.c           |  1 +
 src/mainboard/iei/kino-780am2-fam10/romstage.c       |  1 +
 src/mainboard/jetway/pa78vm5/romstage.c              |  1 +
 src/mainboard/msi/ms9652_fam10/romstage.c            |  1 +
 src/mainboard/supermicro/h8dmr_fam10/romstage.c      |  1 +
 src/mainboard/supermicro/h8qme_fam10/romstage.c      |  1 +
 src/mainboard/supermicro/h8scm_fam10/romstage.c      |  1 +
 src/mainboard/tyan/s2912_fam10/romstage.c            |  1 +
 src/northbridge/amd/amdfam10/Kconfig                 |  1 -
 src/northbridge/amd/amdfam10/northbridge.c           |  3 ---
 src/southbridge/amd/sb700/early_setup.c              |  5 +++++
 src/southbridge/amd/sb700/lpc.c                      |  5 +++++
 src/southbridge/amd/sb800/early_setup.c              |  5 +++++
 27 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/src/cpu/amd/model_10xxx/ram_calc.c b/src/cpu/amd/model_10xxx/ram_calc.c
index 98b80e9..dcf4300 100644
--- a/src/cpu/amd/model_10xxx/ram_calc.c
+++ b/src/cpu/amd/model_10xxx/ram_calc.c
@@ -22,6 +22,8 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
+#include <cbmem.h>
+
 #include "ram_calc.h"
uint64_t get_uma_memory_size(uint64_t topmem)
@@ -41,3 +43,12 @@ uint64_t get_uma_memory_size(uint64_t topmem)
return uma_size;
 }
+
+void *cbmem_top(void)
+{
+	uint32_t topmem = rdmsr(TOP_MEM).lo;
+
+	topmem = topmem - get_uma_memory_size(topmem);
+
+	return (void *) topmem;
+}
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 19ce53e..c1c9a1b 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index d8a38d7..6d03685 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -198,6 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index e6d7f2e..e53c64d 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 76bc73f..ef15e83 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -312,6 +312,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index b7f6869..7d2f272 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 0dab8e8..44864f6 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -343,6 +343,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
printk(BIOS_DEBUG, "disable_spd()\n");
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 7c93767..47b9c83 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 328955a..7ebec29 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -202,6 +202,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index baa38ac..2339478 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index b586198..c1dbaa7 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -201,6 +201,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 4ad3d2c..7b0168d 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 590bb93..d0d6c94 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -197,6 +197,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index a7b6b1b..8861ab6 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index d7e8447..4aefcd2 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -204,6 +204,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
bcm5785_early_setup();
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index b88baa3..991cd55 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -200,6 +200,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 08b6398..df30a69 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -205,6 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 45f05a5..0bdcd38 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -231,6 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index bc1ca24..4615465 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -228,6 +228,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 2be09bc..c8ed2df 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -292,6 +292,7 @@ post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
  raminit_amdmct(sysinfo);
+ cbmem_initialize_empty();
  post_code(0x41);
post_cache_as_ram();  // BSP switch stack to ram, copy then execute LB.
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index eb38a29..4c6292f 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -212,6 +212,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
/*
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 74c0aaa..7dcca17 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -227,6 +227,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "raminit_amdmct()\n");
    raminit_amdmct(sysinfo);
+	cbmem_initialize_empty();
    post_code(0x41);
post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig
index ff7fb9c..37993aa 100644
--- a/src/northbridge/amd/amdfam10/Kconfig
+++ b/src/northbridge/amd/amdfam10/Kconfig
@@ -26,7 +26,6 @@ config NORTHBRIDGE_AMD_AMDFAM10
    select HYPERTRANSPORT_PLUGIN_SUPPORT
    select MMCONF_SUPPORT
    select PER_DEVICE_ACPI_TABLES
-	select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_AMDFAM10
 config AGP_APERTURE_SIZE
diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c
index 68c6e35..9206de7 100644
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -897,10 +897,7 @@ static void amdfam10_domain_set_resources(device_t dev)
    }
#if CONFIG_GFXUMA
-	set_top_of_ram(uma_memory_base);
    uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10);
-#else
-	set_top_of_ram(bsp_topmem());
 #endif
for(link = dev->link_list; link; link = link->next) {
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 94f33b7..0c37840 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -728,6 +728,10 @@ int acpi_get_sleep_type(void)
    return ((tmp & (7 << 10)) >> 10);
 }
+/* FIXME
+ * Remove this block when all processors support early CBMEM init
+ */
+#if CONFIG_LATE_CBMEM_INIT
 unsigned long get_top_of_ram(void)
 {
    uint32_t xdata = 0;
@@ -742,5 +746,6 @@ unsigned long get_top_of_ram(void)
    }
    return (unsigned long) xdata;
 }
+#endif
#endif
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 658e954..a5f11a6 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -88,6 +88,10 @@ int acpi_get_sleep_type(void)
    return ((tmp & (7 << 10)) >> 10);
 }
+/* FIXME
+ * Remove this block when all processors support early CBMEM init
+ */
+#if CONFIG_LATE_CBMEM_INIT
 void backup_top_of_ram(uint64_t ramtop)
 {
    u32 dword = (u32) ramtop;
@@ -98,6 +102,7 @@ void backup_top_of_ram(uint64_t ramtop)
    	nvram_pos++;
    }
 }
+#endif
static void sb700_lpc_read_resources(device_t dev)
 {
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index 69bc3bd..300b54e 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -673,6 +673,10 @@ int acpi_get_sleep_type(void)
    return ((tmp & (7 << 10)) >> 10);
 }
+/* FIXME
+ * Remove this block when all processors support early CBMEM init
+ */
+#if CONFIG_LATE_CBMEM_INIT
 unsigned long get_top_of_ram(void)
 {
    uint32_t xdata = 0;
@@ -687,5 +691,6 @@ unsigned long get_top_of_ram(void)
    }
    return (unsigned long) xdata;
 }
+#endif
#endif

    