Change in coreboot[master]: src/cpu: Fix typo

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27918

Change subject: src/cpu: Fix typo
......................................................................

src/cpu: Fix typo

Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/intel/fsp_model_206ax/finalize.c
M src/cpu/intel/haswell/finalize.c
M src/cpu/intel/model_2065x/finalize.c
M src/cpu/intel/model_206ax/finalize.c
M src/cpu/x86/16bit/entry16.inc
5 files changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/27918/1

diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c
index 53a6cc9..2d5973b 100644
--- a/src/cpu/intel/fsp_model_206ax/finalize.c
+++ b/src/cpu/intel/fsp_model_206ax/finalize.c
@@ -69,7 +69,7 @@
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif

-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);

/* Lock memory configuration to protect SMM */
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index ba25387..ce22e62 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -72,7 +72,7 @@
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif

-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);

/* Lock memory configuration to protect SMM */
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
index 5e7b3d8..8425f6a 100644
--- a/src/cpu/intel/model_2065x/finalize.c
+++ b/src/cpu/intel/model_2065x/finalize.c
@@ -52,6 +52,6 @@
    if (cpuid_ecx(1) & (1 << 25))
    	msr_set_bit(MSR_FEATURE_CONFIG, 0);

-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);
 }
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 50f4977..7d3cc2e 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -70,7 +70,7 @@
    msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
 #endif

-	/* Lock TM interupts - route thermal events to all processors */
+	/* Lock TM interrupts - route thermal events to all processors */
    msr_set_bit(MSR_MISC_PWR_MGMT, 22);

/* Lock memory configuration to protect SMM */
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index a87ce75..5a9739c 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -89,7 +89,7 @@
     * must be loaded at or above 0xffff0000 or below 0x100000.
     *
     * The linker scripts computes gdtptr16_offset by simply returning
-	 * the low 16 bits.  This means that the intial segment used
+	 * the low 16 bits.  This means that the initial segment used
     * when start is called must be 64K aligned.  This should not
     * restrict the address as the ip address can be anything.
     *