Change in coreboot[master]: Documentation/mainboard: Add emulation/spike-riscv.md

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28874 )

Change subject: Documentation/mainboard: Add emulation/spike-riscv.md
......................................................................

Documentation/mainboard: Add emulation/spike-riscv.md

Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.

Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer 
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
Reviewed-by: Philipp Hug 
---
A Documentation/mainboard/emulation/spike-riscv.md
M Documentation/mainboard/index.md
M src/mainboard/emulation/spike-riscv/Kconfig.name
3 files changed, 29 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved
  Philipp Hug: Looks good to me, but someone else must approve

diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md
new file mode 100644
index 0000000..55e87d9
--- /dev/null
+++ b/Documentation/mainboard/emulation/spike-riscv.md
@@ -0,0 +1,23 @@
+# Spike RISC-V emulator
+
+[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.
+
+
+## Installation
+
+- Download `riscv-fesvr` and `riscv-isa-sim` from https://github.com/riscv/
+- Apply the two patches in https://github.com/riscv/riscv-isa-sim/pull/53,
+  which are necessary in order to have a serial console
+- Compile `riscv-fesvr` and then `riscv-isa-sim`
+
+
+## Building coreboot and running it in Spike
+
+- Configure coreboot and run `make` as usual
+- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
+  convert coreboot to an ELF that Spike can load
+- Run `spike -m1024 build/coreboot.elf`
+
+
+[Spike]: https://github.com/riscv/riscv-isa-sim
+[RISC-V]: https://riscv.org/
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index c346a3b..c1e5262 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -10,6 +10,12 @@

- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)

+## Emulation
+
+The boards in this section are not real mainboards, but emulators.
+
+- [Spike RISC-V emulator](emulation/spike-riscv.md)
+
 ## Foxconn

- [D41S](foxconn/d41s.md)
diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name
index 3a82ab1..17549c6 100644
--- a/src/mainboard/emulation/spike-riscv/Kconfig.name
+++ b/src/mainboard/emulation/spike-riscv/Kconfig.name
@@ -1,7 +1,3 @@
 config BOARD_EMULATION_SPIKE_RISCV
    bool "SPIKE riscv"
    help
-	  To run coreboot in spike:
-	  * run "make" as usual
-	  * util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
-	  * spike -m1024 build/coreboot.elf