[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

[Ravishankar Sarawadi (Code Review)]

Attention is currently required from: Bora Guvendik, Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun, Utkarsh H Patel.

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email )

Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
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Patch Set 9:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/78163/comment/f8d75237_2f9cf5c5 :
PS6, Line 14:
> Please mention the datasheet name and revision.

I am still working internally to get supporting doc, these REG offsets are Intel reserved is what I have understood.

Patchset:

PS6:
> > This change is not part of any doc, but I will let you if could get some reference. […]

I am still working internally to get supporting doc, these REG offsets are Intel reserved is what I have understood.

I have raised a partner bug b:306026121 which I think we can use to track progress on supporting doc but since this is a critical fix, could we merge it w/o?