Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47240 )
Change subject: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled ......................................................................
sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2.
However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too.
Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47240/1
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 4a245b1..f7d2430 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -645,9 +645,9 @@ pci_and_config32(dev, 0x338, ~(1 << 26)); }
- /* Enable LTR in Root Port. */ - pci_or_config32(dev, 0x64, 1 << 11); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + /* Enable LTR in Root Port. Disable OBFF. */ + pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11); + pci_update_config32(dev, 0x68, ~(3 << 13), 1 << 10);
pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
Hello Nico Huber, Tristan Corrick, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47240
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled ......................................................................
sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2.
However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too.
Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47240/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47240 )
Change subject: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47240 )
Change subject: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled ......................................................................
sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2.
However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too.
Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47240 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 4a245b1..19eb9fa 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -645,9 +645,9 @@ pci_and_config32(dev, 0x338, ~(1 << 26)); }
- /* Enable LTR in Root Port. */ - pci_or_config32(dev, 0x64, 1 << 11); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + /* Enable LTR in Root Port. Disable OBFF. */ + pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11); + pci_update_config16(dev, 0x68, ~(3 << 13), 1 << 10);
pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
-
Angel Pons (Code Review) -
Nico Huber (Code Review)