[S] Change in coreboot[master]: soc/intel/jasperlake: Enable early caching of RAMTOP region - coreboot-gerrit

1 May 2023


      Attention is currently required from: Sean Rhodes, Matt DeVillier.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74518 )
Change subject: soc/intel/jasperlake: Enable early caching of RAMTOP region
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Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74518/comment/b0162b10_b2ab1e29 
PS4, Line 12: Purpose of this feature is to cache the TOM (with a fixed size of
            : 16MB)
...
same Q as with CML, how does this affect boards with a 32MB flash?
should be applicable for all Intel platform where the BIOS region(16MB) can be cached.
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216
Gerrit-Change-Number: 74518
Gerrit-PatchSet: 4
Gerrit-Owner: Sean Rhodes sean@starlabs.systems
Gerrit-Reviewer: Lean Sheng Tan sheng.tan@9elements.com
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