Attention is currently required from: Patrick Rudolph. Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56011 )
Change subject: soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine ......................................................................
soc/intel/jasperlake: Switch to runtime generation of Intel Power Engine
The pep.asl file is being obsoleted by runtime generation, therefore switch jasperlake boards to this method.
soc/intel/jasperlake: Switch to acpigen PEPD
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ib7f17f9b3b1396708ba68fa7a6d199d6e8b0ba11 --- M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/jasperlake/pmc.c 3 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/56011/1
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index a05cd72..0490d43 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -42,6 +42,7 @@ select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI diff --git a/src/soc/intel/jasperlake/acpi/southbridge.asl b/src/soc/intel/jasperlake/acpi/southbridge.asl index e623cc3..93e538e 100644 --- a/src/soc/intel/jasperlake/acpi/southbridge.asl +++ b/src/soc/intel/jasperlake/acpi/southbridge.asl @@ -44,9 +44,6 @@ /* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl>
-/* Intel Power Engine Plug-in */ -#include <soc/intel/common/block/acpi/acpi/pep.asl> - /* EMMC/SD card */ #include "scs.asl"
diff --git a/src/soc/intel/jasperlake/pmc.c b/src/soc/intel/jasperlake/pmc.c index dce791c..a081d64 100644 --- a/src/soc/intel/jasperlake/pmc.c +++ b/src/soc/intel/jasperlake/pmc.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> +#include <intelblocks/acpi.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> @@ -106,4 +107,7 @@ .set_resources = noop_set_resources, .init = soc_acpi_mode_init, .enable = pmc_init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt = generate_acpi_power_engine, +#endif };