Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40585 )
Change subject: soc/intel/tigerlake: Add SoundWire ACPI support ......................................................................
Patch Set 3:
(3 comments)
This is a mix of mainboard and SOC and really doesn't belong in static ASL in the SOC directory. The code tries to support things like 2 crystal frequencies, but ends up hardcoding for one.
This really needs to be generated this so we can support it properly across boards.
https://review.coreboot.org/c/coreboot/+/40585/3/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/hda_soundwire_ctrl.asl:
https://review.coreboot.org/c/coreboot/+/40585/3/src/soc/intel/tigerlake/acp... PS3, Line 157: SWQx - PCH NVS variables set in accordance with PchPolicy (AudioLinkSndwX) NVS is not being used...
https://review.coreboot.org/c/coreboot/+/40585/3/src/soc/intel/tigerlake/acp... PS3, Line 166: XTAL this seems to be just hardcoding 38.4MHz
https://review.coreboot.org/c/coreboot/+/40585/3/src/soc/intel/tigerlake/acp... PS3, Line 175: PCH NVS NVS is not being used...
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Duncan Laurie (Code Review)