Change in ...coreboot[master]: rockchip: rk3399: increase heap and memory for fit payload.
Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32373
Change subject: rockchip: rk3399: increase heap and memory for fit payload. ......................................................................
rockchip: rk3399: increase heap and memory for fit payload.
Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer hanetzer@startmail.com --- M src/soc/rockchip/rk3399/Kconfig M src/soc/rockchip/rk3399/include/soc/memlayout.ld 2 files changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32373/1
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 6e45df3..67e36ff 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -34,4 +34,7 @@ used to modulate the frequency of the Silicon Creations' Fractional PLL in order to reduce EMI.
+config HEAP_SIZE + default 0x100000 + endif diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 73fc499..f2512b0 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -20,8 +20,8 @@ { DRAM_START(0x00000000) BL31(0, 0x100000) - POSTRAM_CBFS_CACHE(0x00100000, 1M) - RAMSTAGE(0x00300000, 256K) + POSTRAM_CBFS_CACHE(0x00100000, 16M) + RAMSTAGE(0x01100000, 2M) DMA_COHERENT(0x10000000, 2M)
/* 8K of special SRAM in PMU power domain. */
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase heap and memory for fit payload. ......................................................................
Patch Set 1:
Unsure exactly how to phrase this. I basically was just tooling around based on the cavium support for fit images as prompted by siro__ on irc, and to be quite frank I don't know coreboot's guts enough to actually understand why this works and whatnot. Someone more well versed may want to redo this in a better way, but these changes let me boot a uImage.FIT on my gru-kevin chromebook. The petitboot part of what I'm doing doesn't work yet, however.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase heap and memory for fit payload. ......................................................................
Patch Set 1: Code-Review+1
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase heap and memory for fit payload. ......................................................................
Patch Set 1:
I don't think the Kconfig change belongs here since there's nothing Rockchip-specific about it... it's just that the FIT code may use a lot more heap than the coreboot default expects.
How about we just change src/Kconfig to read
config HEAP_SIZE hex default 0x100000 if FLATTENED_DEVICE_TREE default 0x4000
? Then it works for all boards that enable FIT support out of the box.
You can still submit a separate change to increase the ramstage in rk3399's memlayout, that doesn't hurt anyone.
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase heap and memory for fit payload. ......................................................................
Patch Set 1:
Patch Set 1:
I don't think the Kconfig change belongs here since there's nothing Rockchip-specific about it... it's just that the FIT code may use a lot more heap than the coreboot default expects.
How about we just change src/Kconfig to read
config HEAP_SIZE hex default 0x100000 if FLATTENED_DEVICE_TREE default 0x4000
? Then it works for all boards that enable FIT support out of the box.
You can still submit a separate change to increase the ramstage in rk3399's memlayout, that doesn't hurt anyone.
So remove the Kconfig edit on this patchset and do another for the HEAP_SIZE in the 'global' kconfig?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase heap and memory for fit payload. ......................................................................
Patch Set 1:
So remove the Kconfig edit on this patchset and do another for the HEAP_SIZE in the 'global' kconfig?
Exactly.
Hello Lin Huang, Patrick Rudolph, nickey yang, Julius Werner, Ting Shen, build bot (Jenkins), Vadim Bendebury, Shunqian Zheng,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32373
to look at the new patch set (#2).
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
rockchip: rk3399: increase memory for fit payload.
Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer hanetzer@startmail.com --- M src/soc/rockchip/rk3399/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32373/2
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/32373/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32373/2//COMMIT_MSG@7 PS2, Line 7: rockchip: rk3399: increase memory for fit payload. nit: Please be a little clearer about what you're changing and why, e.g.
rockchip/rk3399: Increase size reserved for ramstage to 2MB
This patch increases the size reserved for the ramstage in memlayout to 2MB because ...
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... File src/soc/rockchip/rk3399/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 23: 16M Why would this need to change?
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 24: 1100000 Why change the base address? (2M would've still easily fit where it was before.)
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... File src/soc/rockchip/rk3399/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 23: 16M
Why would this need to change?
I forget exactly, but someone mentioned increasing/adding a POSTRAM_CBFS_CACHE, see src/soc/cavium/cn81xx/include/soc/memlayout.ld:51
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 24: 1100000
Why change the base address? (2M would've still easily fit where it was before. […]
Unless I'm mistaken, the first parameter is an address in 'normal' dram and they're sequential (BL31 starts at 0 and extends 0x100000 bytes, and POSTRAM_CBFS_CACHE starts at 0x100000, the end of BL31, so I added 16*1024*1024 to the starting address of POSTRAM_CBFS_CACHE and 'moved' the RAMSTAGE there.
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Patch Set 1:
So remove the Kconfig edit on this patchset and do another for the HEAP_SIZE in the 'global' kconfig?
Exactly.
Should that dep on FLATTENED_DEVICE_TREE or maybe PAYLOAD_FIT_SUPPORT or maybe even PAYLOAD_FIT ?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... File src/soc/rockchip/rk3399/include/soc/memlayout.ld:
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 23: 16M
I forget exactly, but someone mentioned increasing/adding a POSTRAM_CBFS_CACHE, […]
I know there needs to be a postram cache but there should be no reason for it to be 16MB. It has nothing to do with loading FIT payloads.
Please don't change this unless there's an actual reason for it so that your patch can stay single-purpose.
https://review.coreboot.org/#/c/32373/2/src/soc/rockchip/rk3399/include/soc/... PS2, Line 24: 1100000
Unless I'm mistaken, the first parameter is an address in 'normal' dram and they're […]
Okay, fair enough, but if you don't change the postram cache you also won't need to change this.
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Increasing the ramstage to 2M (1M is not enough) is required to even build with the uImage embedded, otherwise you get
coreboot/util/crossgcc/xgcc/bin/aarch64-elf-ld.bfd: Ramstage exceeded its allotted size! (256K) make: *** [src/arch/arm64/Makefile.inc:154: build/cbfs/fallback/ramstage.debug] Error 1
After making this change, flashing and cold resetting, you get this:
CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1a000 size 6f6a58 Payload not loaded.
Increasing the POSTRAM_CBFS_CACHE to 2M has the same results. 3M requires moving the RAMSTAGE, and has the same results. 4M has the same results. 5M has the same results. 6M has the same results. 7M is the minimal required size (assuming 1M increments) to get the payload booting in the first place, though a further change to the uImage required me to bump it to 8M.
So, what are your suggestions?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2: Code-Review+2
After making this change, flashing and cold resetting, you get this:
CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1a000 size 6f6a58 Payload not loaded.
Okay, sorry, I re-read the FIT code and I realize why you need this now. I also don't see a simple way to improve it (we have to allocate the loaded FIT image somewhere, and the heap isn't going to be big enough either, so might as well use the CBFS cache I guess). We can take this patch as is.
Maybe you could add an error message to fit_payload() (the if (data == NULL) check at the top) that makes it more obvious to the user that they need to increase their CBFS cache? "Payload not loaded" alone is not very helpful.
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Currently having an issue; was 'working' (as far as booting the embedded uImage) but now I'm stuck in coreboot land with the following:
coreboot-4.9-1422-g0987e43aa0-dirty Wed Apr 24 20:42:52 UTC 2019 bootblock starting (log level: 7)... ARM64: Exception handlers installed. PLL at 00000000ff750000: fbdiv=169, refdiv=3, postdiv1=2, postdiv2=1, vco=1352000 khz, output=676000 khz PLL at 00000000ff760080: fbdiv=99, refdiv=1, postdiv1=4, postdiv2=1, vco=2376000 khz, output=594000 khz PLL at 00000000ff760060: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz ADC reading 581, ID 8 PLL at 00000000ff760000: fbdiv=63, refdiv=1, postdiv1=1, postdiv2=1, vco=1512000 khz, output=1512000 khz I2C bus 0: 398584Hz (divh = 44, divl = 60) Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 6339
coreboot-4.9-1422-g0987e43aa0-dirty Wed Apr 24 20:42:52 UTC 2019 romstage starting (log level: 7)... ARM64: Exception handlers installed. ADC reading 581, ID 8 Starting DWC3 and TCPHY reset for USB OTG0 Starting DWC3 and TCPHY reset for USB OTG1 ADC reading 62, ID 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'sdram-lpddr3-generic-4GB-928' CBFS: Found @ offset 710ac0 size 374 Starting SDRAM initialization... PLL at 00000000ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Finish SDRAM initialization... Mapping address range [0000000000000000:00000000f8000000) as cacheable | read-write | non-secure | normal Mapping address range [0000000010000000:0000000010200000) as non-cacheable | read-write | non-secure | normal Backing address range [0000000000000000:0000000040000000) with new page table @00000000ff8e9000 CBMEM: IMD: root @ 00000000f7fff000 254 entries. IMD: root @ 00000000f7ffec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 6400 size b761
coreboot-4.9-1422-g0987e43aa0-dirty Wed Apr 24 20:42:52 UTC 2019 ramstage starting (log level: 7)... ARM64: Exception handlers installed. BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 1 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 1 Enumerating buses... CPU_CLUSTER: 0 enabled scan_bus: scanning of bus Root Device took 2092 usecs done BS: BS_DEV_ENUMERATE times (us): entry 1 run 9315 exit 1 Allocating resources... Reading resources... Done reading resources. Setting resources... CPU_CLUSTER: 0 missing set_resources Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 1 run 16107 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 0 run 2620 exit 0 tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms I2C TPM 0:20 (chip type slb9645tt device-id 0x1A) TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded Initializing devices... Root Device init ... DWC3 and TCPHY setup for USB OTG0 finished out: cmd=0x101: 03 f4 01 01 00 00 04 00 00 03 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 out: cmd=0x101: 03 f6 01 01 00 00 04 00 00 01 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 DWC3 and TCPHY setup for USB OTG1 finished out: cmd=0x101: 03 f3 01 01 00 00 04 00 01 03 00 00 in-header: 03 f2 00 00 04 00 00 00 in-data: 00 00 01 06 out: cmd=0x101: 03 f5 01 01 00 00 04 00 01 01 00 00 in-header: 03 f2 00 00 04 00 00 00 in-data: 00 00 01 06 Root Device init finished in 74077 usecs CPU_CLUSTER: 0 init ... Attempting to set up EDP display. PLL at 00000000ff7600c0: fbdiv=337, refdiv=8, postdiv1=4, postdiv2=1, vco=1011000 khz, output=252750 khz clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 PLL at 00000000ff760020: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz CPU_CLUSTER: 0 init finished in 126107 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 63395 run 211841 exit 1 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 3488 exit 1 BS: BS_OS_RESUME_CHECK times (us): entry 1 run 1 exit 0 Writing coreboot table at 0xf7fdc000 0. 0000000000000000-00000000000fffff: BL31 1. 0000000000100000-00000000001fffff: RAMSTAGE 2. 0000000000200000-00000000002fffff: RAM 3. 0000000000300000-000000000041efff: RAMSTAGE 4. 000000000041f000-00000000f7fdbfff: RAM 5. 00000000f7fdc000-00000000f7ffffff: CONFIGURATION TABLES 6. 00000000ff3b0000-00000000ff3b1fff: BL31 7. 00000000ff8c0000-00000000ff8cffff: BL31 8. 00000000ff8e5000-00000000ff8eafff: RAMSTAGE 9. 00000000ff8ed000-00000000ff8effff: RAMSTAGE ADC reading 580, ID 8 Board ID: 8 ADC reading 62, ID 0 RAM code: 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) FMAP: Found "FLASH" version 1.1 at 20000. FMAP: base = 0 size = 800000 #areas = 4 Wrote coreboot table at: 00000000f7fdc000, 0x1f8 bytes, checksum d5f2 coreboot table: 528 bytes. IMD ROOT 0. 00000000f7fff000 00001000 IMD SMALL 1. 00000000f7ffe000 00001000 CONSOLE 2. 00000000f7fde000 00020000 COREBOOT 3. 00000000f7fdc000 00002000 IMD small region: IMD ROOT 0. 00000000f7ffec00 00000400 BS: BS_WRITE_TABLES times (us): entry 0 run 102826 exit 1 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1a000 size 6f6a58 Payload not loaded.
Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Disregard the above log, somehow got the wrong one. This is what is currently happening:
coreboot-4.9-1423-g97d4614237-dirty Wed Apr 24 21:27:58 UTC 2019 bootblock starting (log level: 7)... ARM64: Exception handlers installed. PLL at 00000000ff750000: fbdiv=169, refdiv=3, postdiv1=2, postdiv2=1, vco=1352000 khz, output=676000 khz PLL at 00000000ff760080: fbdiv=99, refdiv=1, postdiv1=4, postdiv2=1, vco=2376000 khz, output=594000 khz PLL at 00000000ff760060: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz ADC reading 581, ID 8 PLL at 00000000ff760000: fbdiv=63, refdiv=1, postdiv1=1, postdiv2=1, vco=1512000 khz, output=1512000 khz I2C bus 0: 398584Hz (divh = 44, divl = 60) Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 6338
coreboot-4.9-1423-g97d4614237-dirty Wed Apr 24 21:27:58 UTC 2019 romstage starting (log level: 7)... ARM64: Exception handlers installed. ADC reading 581, ID 8 Starting DWC3 and TCPHY reset for USB OTG0 Starting DWC3 and TCPHY reset for USB OTG1 ADC reading 62, ID 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'sdram-lpddr3-generic-4GB-928' CBFS: Found @ offset 747980 size 374 Starting SDRAM initialization... PLL at 00000000ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Finish SDRAM initialization... Mapping address range [0000000000000000:00000000f8000000) as cacheable | read-write | non-secure | normal Mapping address range [0000000010000000:0000000010200000) as non-cacheable | read-write | non-secure | normal Backing address range [0000000000000000:0000000040000000) with new page table @00000000ff8e9000 CBMEM: IMD: root @ 00000000f7fff000 254 entries. IMD: root @ 00000000f7ffec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 6400 size b76b
coreboot-4.9-1423-g97d4614237-dirty Wed Apr 24 21:27:58 UTC 2019 ramstage starting (log level: 7)... ARM64: Exception handlers installed. BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 1 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 1 Enumerating buses... CPU_CLUSTER: 0 enabled scan_bus: scanning of bus Root Device took 2091 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 9319 exit 0 Allocating resources... Reading resources... Done reading resources. Setting resources... CPU_CLUSTER: 0 missing set_resources Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 1 run 16111 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 1 run 2620 exit 1 tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms I2C TPM 0:20 (chip type slb9645tt device-id 0x1A) TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded Initializing devices... Root Device init ... DWC3 and TCPHY setup for USB OTG0 finished out: cmd=0x101: 03 f4 01 01 00 00 04 00 00 03 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 out: cmd=0x101: 03 f6 01 01 00 00 04 00 00 01 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 DWC3 and TCPHY setup for USB OTG1 finished out: cmd=0x101: 03 f3 01 01 00 00 04 00 01 03 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 out: cmd=0x101: 03 f5 01 01 00 00 04 00 01 01 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 Root Device init finished in 77359 usecs CPU_CLUSTER: 0 init ... Attempting to set up EDP display. PLL at 00000000ff7600c0: fbdiv=337, refdiv=8, postdiv1=4, postdiv2=1, vco=1011000 khz, output=252750 khz clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 PLL at 00000000ff760020: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz CPU_CLUSTER: 0 init finished in 126083 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 63375 run 215097 exit 1 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 1 run 3486 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 1 run 0 exit 1 Writing coreboot table at 0xf7fdc000 0. 0000000000000000-00000000000fffff: BL31 1. 0000000000100000-0000000000a1efff: RAMSTAGE 2. 0000000000a1f000-00000000f7fdbfff: RAM 3. 00000000f7fdc000-00000000f7ffffff: CONFIGURATION TABLES 4. 00000000ff3b0000-00000000ff3b1fff: BL31 5. 00000000ff8c0000-00000000ff8cffff: BL31 6. 00000000ff8e5000-00000000ff8eafff: RAMSTAGE 7. 00000000ff8ed000-00000000ff8effff: RAMSTAGE ADC reading 581, ID 8 Board ID: 8 ADC reading 62, ID 0 RAM code: 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) FMAP: Found "FLASH" version 1.1 at 20000. FMAP: base = 0 size = 800000 #areas = 4 Wrote coreboot table at: 00000000f7fdc000, 0x1f8 bytes, checksum f07d coreboot table: 528 bytes. IMD ROOT 0. 00000000f7fff000 00001000 IMD SMALL 1. 00000000f7ffe000 00001000 CONSOLE 2. 00000000f7fde000 00020000 COREBOOT 3. 00000000f7fdc000 00002000 IMD small region: IMD ROOT 0. 00000000f7ffec00 00000400 BS: BS_WRITE_TABLES times (us): entry 0 run 94740 exit 0 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1a000 size 72d928 FIT: Examine payload fallback/payload FIT: Loading FIT from 0000000000100000 FIT: Image ramdisk-1 has 2450076 bytes. FIT: Image fdt-1 has 61032 bytes. FIT: Image kernel has 5013356 bytes. FIT: Compat preference (lowest to highest priority) : google,kevin google,kevin-rev8 FIT: config conf-1 (default), fdt fdt-1, ramdisk ramdisk-1, compat google,kevin-rev15 google,kevin-rev14 google,kevin-rev13 google,kevin-rev12 google,kevin-rev11 google,kevin-rev10 google,kevin-rev9 google,kevin-rev8 google,kevin-rev7 google,kevin-rev6 google,kevin (match) google,gru rockchip,rk3399 FIT: Choosing best match conf-1 for compat google,kevin. FIT: Updating devicetree memory entries FIT: Using kernel size of 0xfe4000 bytes FIT: Placing FDT and INITRD anywhere 0. 0000000000000000-00000000000fffff: BL31 1. 0000000000100000-0000000000a1efff: RAMSTAGE 2. 0000000000a1f000-0000000000a7ffff: RAM 3. 0000000000a80000-0000000001a63fff: PAYLOAD 4. 0000000001a64000-0000000001afffff: RAM 5. 0000000001b00000-0000000001d56fff: PAYLOAD 6. 0000000001d57000-0000000001dfffff: RAM 7. 0000000001e00000-0000000001e13fff: PAYLOAD 8. 0000000001e14000-00000000f7fdbfff: RAM 9. 00000000f7fdc000-00000000f7ffffff: CONFIGURATION TABLES 10. 00000000ff3b0000-00000000ff3b1fff: BL31 11. 00000000ff8c0000-00000000ff8cffff: BL31 12. 00000000ff8e5000-00000000ff8eafff: RAMSTAGE 13. 00000000ff8ed000-00000000ff8effff: RAMSTAGE FIT: Flattening FDT to 0000000001e00000 FIT: Relocating uncompressed ramdisk-1 to 0000000001b00000 FIT: Decompressing LZMA kernel to 0000000000a80000 BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2889445 exit 1 Jumping to boot code at 0000000000a80000(0000000001e00000) CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 11fc0 size 8000 Checking segment from ROM address 0x0000000000100000 Checking segment from ROM address 0x000000000010001c Checking segment from ROM address 0x0000000000100038 Checking segment from ROM address 0x0000000000100054 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x0000000000000000 memsize 0x33000 srcaddr 0x0000000000100070 filesize 0x7564 Loading Segment: addr: 0x0000000000000000 memsz: 0x0000000000033000 filesz: 0x0000000000007564 using LZMA Clearing Segment: addr: 0x0000000000013029 memsz: 0x000000000001ffd7 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0x00000000ff3b0000 memsize 0x1a20 srcaddr 0x00000000001075d4 filesize 0x85f Loading Segment: addr: 0x00000000ff3b0000 memsz: 0x0000000000001a20 filesz: 0x000000000000085f using LZMA Loading segment from ROM address 0x0000000000100038 code (compression=1) New segment dstaddr 0x00000000ff8c0000 memsize 0x3000 srcaddr 0x0000000000107e33 filesize 0x1cd Loading Segment: addr: 0x00000000ff8c0000 memsz: 0x0000000000003000 filesz: 0x00000000000001cd using LZMA Clearing Segment: addr: 0x00000000ff8c2000 memsz: 0x0000000000001000 Loading segment from ROM address 0x0000000000100054 Entry Point 0x0000000000001000 NOTICE: BL31: v1.4(release):v1.4-600-g693e278e NOTICE: BL31: Built : Wed Apr 24 21:27:58 UTC 2019 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1612): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa80000 INFO: SPSR = 0x8
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Please update the commit message as Julius requested.
Hello Lin Huang, Patrick Rudolph, nickey yang, Julius Werner, build bot (Jenkins), Ting Shen, Vadim Bendebury, Shunqian Zheng,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32373
to look at the new patch set (#3).
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
rockchip: rk3399: increase memory for fit payload.
Increase ramstage to 2M, required to actually embed the 7.2mb uImage into the coreboot.rom, increase the postram cbfs cache in order for the fit image to be loadable (without this increase the fit payload is found but not loaded)
Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer hanetzer@startmail.com --- M src/soc/rockchip/rk3399/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32373/3
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 3: Code-Review+2
Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
rockchip: rk3399: increase memory for fit payload.
Increase ramstage to 2M, required to actually embed the 7.2mb uImage into the coreboot.rom, increase the postram cbfs cache in order for the fit image to be loadable (without this increase the fit payload is found but not loaded)
Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2 Signed-off-by: Marty E. Plummer hanetzer@startmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32373 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/soc/rockchip/rk3399/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index 73fc499..293057a 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -20,8 +20,8 @@ { DRAM_START(0x00000000) BL31(0, 0x100000) - POSTRAM_CBFS_CACHE(0x00100000, 1M) - RAMSTAGE(0x00300000, 256K) + POSTRAM_CBFS_CACHE(0x00100000, 8M) + RAMSTAGE(0x00900000, 2M) DMA_COHERENT(0x10000000, 2M)
/* 8K of special SRAM in PMU power domain. */
-
Julius Werner (Code Review) -
Marty E. Plummer (Code Review)
-
Patrick Rudolph (Code Review)
-
Paul Menzel (Code Review)