Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Disregard the above log, somehow got the wrong one. This is what is currently happening:
coreboot-4.9-1423-g97d4614237-dirty Wed Apr 24 21:27:58 UTC 2019 bootblock starting (log level: 7)... ARM64: Exception handlers installed. PLL at 00000000ff750000: fbdiv=169, refdiv=3, postdiv1=2, postdiv2=1, vco=1352000 khz, output=676000 khz PLL at 00000000ff760080: fbdiv=99, refdiv=1, postdiv1=4, postdiv2=1, vco=2376000 khz, output=594000 khz PLL at 00000000ff760060: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz ADC reading 581, ID 8 PLL at 00000000ff760000: fbdiv=63, refdiv=1, postdiv1=1, postdiv2=1, vco=1512000 khz, output=1512000 khz I2C bus 0: 398584Hz (divh = 44, divl = 60) Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 6338
coreboot-4.9-1423-g97d4614237-dirty Wed Apr 24 21:27:58 UTC 2019 romstage starting (log level: 7)... ARM64: Exception handlers installed. ADC reading 581, ID 8 Starting DWC3 and TCPHY reset for USB OTG0 Starting DWC3 and TCPHY reset for USB OTG1 ADC reading 62, ID 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'sdram-lpddr3-generic-4GB-928' CBFS: Found @ offset 747980 size 374 Starting SDRAM initialization... PLL at 00000000ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Finish SDRAM initialization... Mapping address range [0000000000000000:00000000f8000000) as cacheable | read-write | non-secure | normal Mapping address range [0000000010000000:0000000010200000) as non-cacheable | read-write | non-secure | normal Backing address range [0000000000000000:0000000040000000) with new page table @00000000ff8e9000 CBMEM: IMD: root @ 00000000f7fff000 254 entries. IMD: root @ 00000000f7ffec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 6400 size b76b
coreboot-4.9-1423-g97d4614237-dirty Wed Apr 24 21:27:58 UTC 2019 ramstage starting (log level: 7)... ARM64: Exception handlers installed. BS: BS_PRE_DEVICE times (us): entry 1 run 0 exit 1 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 1 Enumerating buses... CPU_CLUSTER: 0 enabled scan_bus: scanning of bus Root Device took 2091 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 9319 exit 0 Allocating resources... Reading resources... Done reading resources. Setting resources... CPU_CLUSTER: 0 missing set_resources Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 1 run 16111 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 1 run 2620 exit 1 tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms I2C TPM 0:20 (chip type slb9645tt device-id 0x1A) TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded Initializing devices... Root Device init ... DWC3 and TCPHY setup for USB OTG0 finished out: cmd=0x101: 03 f4 01 01 00 00 04 00 00 03 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 out: cmd=0x101: 03 f6 01 01 00 00 04 00 00 01 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 DWC3 and TCPHY setup for USB OTG1 finished out: cmd=0x101: 03 f3 01 01 00 00 04 00 01 03 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 out: cmd=0x101: 03 f5 01 01 00 00 04 00 01 01 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 Root Device init finished in 77359 usecs CPU_CLUSTER: 0 init ... Attempting to set up EDP display. PLL at 00000000ff7600c0: fbdiv=337, refdiv=8, postdiv1=4, postdiv2=1, vco=1011000 khz, output=252750 khz clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 PLL at 00000000ff760020: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz CPU_CLUSTER: 0 init finished in 126083 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 63375 run 215097 exit 1 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 1 run 3486 exit 0 BS: BS_OS_RESUME_CHECK times (us): entry 1 run 0 exit 1 Writing coreboot table at 0xf7fdc000 0. 0000000000000000-00000000000fffff: BL31 1. 0000000000100000-0000000000a1efff: RAMSTAGE 2. 0000000000a1f000-00000000f7fdbfff: RAM 3. 00000000f7fdc000-00000000f7ffffff: CONFIGURATION TABLES 4. 00000000ff3b0000-00000000ff3b1fff: BL31 5. 00000000ff8c0000-00000000ff8cffff: BL31 6. 00000000ff8e5000-00000000ff8eafff: RAMSTAGE 7. 00000000ff8ed000-00000000ff8effff: RAMSTAGE ADC reading 581, ID 8 Board ID: 8 ADC reading 62, ID 0 RAM code: 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) FMAP: Found "FLASH" version 1.1 at 20000. FMAP: base = 0 size = 800000 #areas = 4 Wrote coreboot table at: 00000000f7fdc000, 0x1f8 bytes, checksum f07d coreboot table: 528 bytes. IMD ROOT 0. 00000000f7fff000 00001000 IMD SMALL 1. 00000000f7ffe000 00001000 CONSOLE 2. 00000000f7fde000 00020000 COREBOOT 3. 00000000f7fdc000 00002000 IMD small region: IMD ROOT 0. 00000000f7ffec00 00000400 BS: BS_WRITE_TABLES times (us): entry 0 run 94740 exit 0 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1a000 size 72d928 FIT: Examine payload fallback/payload FIT: Loading FIT from 0000000000100000 FIT: Image ramdisk-1 has 2450076 bytes. FIT: Image fdt-1 has 61032 bytes. FIT: Image kernel has 5013356 bytes. FIT: Compat preference (lowest to highest priority) : google,kevin google,kevin-rev8 FIT: config conf-1 (default), fdt fdt-1, ramdisk ramdisk-1, compat google,kevin-rev15 google,kevin-rev14 google,kevin-rev13 google,kevin-rev12 google,kevin-rev11 google,kevin-rev10 google,kevin-rev9 google,kevin-rev8 google,kevin-rev7 google,kevin-rev6 google,kevin (match) google,gru rockchip,rk3399 FIT: Choosing best match conf-1 for compat google,kevin. FIT: Updating devicetree memory entries FIT: Using kernel size of 0xfe4000 bytes FIT: Placing FDT and INITRD anywhere 0. 0000000000000000-00000000000fffff: BL31 1. 0000000000100000-0000000000a1efff: RAMSTAGE 2. 0000000000a1f000-0000000000a7ffff: RAM 3. 0000000000a80000-0000000001a63fff: PAYLOAD 4. 0000000001a64000-0000000001afffff: RAM 5. 0000000001b00000-0000000001d56fff: PAYLOAD 6. 0000000001d57000-0000000001dfffff: RAM 7. 0000000001e00000-0000000001e13fff: PAYLOAD 8. 0000000001e14000-00000000f7fdbfff: RAM 9. 00000000f7fdc000-00000000f7ffffff: CONFIGURATION TABLES 10. 00000000ff3b0000-00000000ff3b1fff: BL31 11. 00000000ff8c0000-00000000ff8cffff: BL31 12. 00000000ff8e5000-00000000ff8eafff: RAMSTAGE 13. 00000000ff8ed000-00000000ff8effff: RAMSTAGE FIT: Flattening FDT to 0000000001e00000 FIT: Relocating uncompressed ramdisk-1 to 0000000001b00000 FIT: Decompressing LZMA kernel to 0000000000a80000 BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2889445 exit 1 Jumping to boot code at 0000000000a80000(0000000001e00000) CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 11fc0 size 8000 Checking segment from ROM address 0x0000000000100000 Checking segment from ROM address 0x000000000010001c Checking segment from ROM address 0x0000000000100038 Checking segment from ROM address 0x0000000000100054 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x0000000000000000 memsize 0x33000 srcaddr 0x0000000000100070 filesize 0x7564 Loading Segment: addr: 0x0000000000000000 memsz: 0x0000000000033000 filesz: 0x0000000000007564 using LZMA Clearing Segment: addr: 0x0000000000013029 memsz: 0x000000000001ffd7 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0x00000000ff3b0000 memsize 0x1a20 srcaddr 0x00000000001075d4 filesize 0x85f Loading Segment: addr: 0x00000000ff3b0000 memsz: 0x0000000000001a20 filesz: 0x000000000000085f using LZMA Loading segment from ROM address 0x0000000000100038 code (compression=1) New segment dstaddr 0x00000000ff8c0000 memsize 0x3000 srcaddr 0x0000000000107e33 filesize 0x1cd Loading Segment: addr: 0x00000000ff8c0000 memsz: 0x0000000000003000 filesz: 0x00000000000001cd using LZMA Clearing Segment: addr: 0x00000000ff8c2000 memsz: 0x0000000000001000 Loading segment from ROM address 0x0000000000100054 Entry Point 0x0000000000001000 NOTICE: BL31: v1.4(release):v1.4-600-g693e278e NOTICE: BL31: Built : Wed Apr 24 21:27:58 UTC 2019 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1612): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0xa80000 INFO: SPSR = 0x8