Change in coreboot[master]: nb/intel/i945: Correct SLP_S4# comment

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28395

Change subject: nb/intel/i945: Correct SLP_S4# comment
......................................................................

nb/intel/i945: Correct SLP_S4# comment

Bit #3 of GEN_PMCON_3 register will enable
SLP_S4# Assertion Stretch.

Change-Id: I86df0df5337397d2c23ca311ecae1c8a38eb32f0
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/i945/raminit.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/28395/1

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index c259530..c22d4eb 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -265,7 +265,7 @@
    		do_reset = 1;
    	}

-		/* Set SLP_S3# Assertion Stretch Enable */
+		/* Set SLP_S4# Assertion Stretch Enable */
    	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); /* GEN_PMCON_3 */
    	reg8 |= (1 << 3);
    	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);