[S] Change in coreboot[master]: mb/siemens/mc_ehl1: Limit SATA speed to Gen 2

[Eric Lai (Code Review)]

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71230 )

Change subject: mb/siemens/mc_ehl1: Limit SATA speed to Gen 2
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mb/siemens/mc_ehl1: Limit SATA speed to Gen 2

Due to mainboard restrictions a SATA link at Gen 3 (6 Gbps) can cause
issues as the margin is not big enough. Limit SATA speed to Gen 2 to
achieve a more robust SATA connection.

Change-Id: Ia79998db5f959528a4e8e29e570a7f55283adee1
Signed-off-by: Werner Zeh 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71230
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
Reviewed-by: Mario Scheithauer 
Reviewed-by: Arthur Heymans 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 20 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Mario Scheithauer: Looks good to me, approved
  Arthur Heymans: Looks good to me, approved

diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
index 319a8437..8207078 100644
--- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
@@ -82,6 +82,7 @@
    register "SataPortsEnable[1]" = "1"
    register "SataPortsDevSlp[0]" = "0"
    register "SataPortsDevSlp[1]" = "0"
+	register "SataSpeed" = "SATA_GEN2"

register "ScsEmmcHs400Enabled" = "0"
    register "ScsEmmcDdr50Enabled" = "1"