Change in coreboot[master]: riscv: add support to select the privilege level of the payload running

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/29494

Change subject: riscv: add support to select the privilege level of the payload running
......................................................................

riscv: add support to select the privilege level of the payload running

Change-Id: I96961246cd257b63cf167238aa0cf6e65272b951
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
M src/arch/riscv/boot.c
M src/arch/riscv/include/arch/boot.h
D src/arch/riscv/payload.S
A src/arch/riscv/payload.c
6 files changed, 79 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/29494/1

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index ae83be8..aeaed32 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -38,3 +38,25 @@

config RISCV_WORKING_HARTID
    int
+
+config RISCV_PAYLOAD_MODE
+	int
+	default 0 if RISCV_PAYLOAD_U_MODE
+	default 1 if RISCV_PAYLOAD_S_MODE
+	default 3 if RISCV_PAYLOAD_M_MODE
+
+choice
+	prompt "***Privilege level for payload***"
+	default RISCV_PAYLOAD_S_MODE
+
+config RISCV_PAYLOAD_U_MODE
+	bool "payload running in u-mode"
+
+
+config RISCV_PAYLOAD_S_MODE
+	bool "payload running in s-mode"
+
+config RISCV_PAYLOAD_M_MODE
+	bool "payload running in m-mode"
+
+endchoice
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index eacf32a..37570f7 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -124,7 +124,7 @@
 ramstage-y += smp.c
 ramstage-y += boot.c
 ramstage-y += tables.c
-ramstage-y += payload.S
+ramstage-y += payload.c
 ramstage-y += pmp.c
 ramstage-y += \
    $(top)/src/lib/memchr.c \
diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c
index 8b8f365..67fbb17 100644
--- a/src/arch/riscv/boot.c
+++ b/src/arch/riscv/boot.c
@@ -34,7 +34,6 @@
 {
    const void *fdt = HLS()->fdt;
    void (*doit)(void *) = prog_entry(prog);
-	void riscvpayload(const void *fdt, void *payload);

if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
    	/*
@@ -45,7 +44,10 @@

printk(BIOS_SPEW, "FDT is at %p\n", fdt);
    	printk(BIOS_SPEW, "OK, let's go\n");
-		riscvpayload(fdt, doit);
+		void (*fn)(uintptr_t arg0, uintptr_t arg1) = prog_entry(prog);
+		uintptr_t arg0 = read_csr(mhartid);
+		uintptr_t arg1 = (uintptr_t)fdt;
+		run_payload(fn, arg0, arg1);
    }

write_csr(mscratch, fdt);
diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h
index 24c1bed..4c9158a 100644
--- a/src/arch/riscv/include/arch/boot.h
+++ b/src/arch/riscv/include/arch/boot.h
@@ -16,6 +16,12 @@
 #ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H
 #define ARCH_RISCV_INCLUDE_ARCH_BOOT_H

+#include <stdint.h>
+
 extern const void *rom_fdt;
+void run_payload(
+		void (*fn)(uintptr_t arg0, uintptr_t arg1),
+			uintptr_t arg0,
+			uintptr_t arg1);

#endif
diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S
deleted file mode 100644
index 1b8cb96..0000000
--- a/src/arch/riscv/payload.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Google Inc
- * Copyright (C) 2018 Jonathan Neuschäfer
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// "return" to a payload. a0: FDT, a1: entry point
-	.global riscvpayload
-riscvpayload:
-	/* Load the entry point */
-	mv	t0, a1
-	csrw	mepc, t0
-	csrr	t0, mstatus
-
-	/* Set mstatus.MPP (the previous privilege mode) to supervisor mode */
-	li	t1, ~(3<<11)
-	and	t0, t0, t1
-	li	t2,  (1<<11)
-	or	t0, t0, t2
-	csrw	mstatus, t0
-
-	/* Pass the right arguments and jump! */
-	mv	a1, a0
-	csrr	a0, mhartid
-	mret
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
new file mode 100644
index 0000000..de87ac7
--- /dev/null
+++ b/src/arch/riscv/payload.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/boot.h>
+#include <arch/encoding.h>
+#include <console/console.h>
+
+void run_payload(
+		void (*fn)(uintptr_t arg0, uintptr_t arg1),
+			uintptr_t arg0,
+			uintptr_t arg1)
+{
+	uintptr_t status = read_csr(mstatus) & ~MSTATUS_MPP;
+	switch (CONFIG_RISCV_PAYLOAD_MODE) {
+	case 0:
+		break;
+	case 1:
+		status |= MSTATUS_SPP;
+		break;
+	case 3:
+		status |= MSTATUS_MPP;
+		break;
+	default:
+		die("wrong privilege level for payload");
+		break;
+	}
+	write_csr(mstatus, status);
+	write_csr(mepc, fn);
+	asm volatile("mv a0, %0"::"r"(arg0):"a0");
+	asm volatile("mv a1, %0"::"r"(arg1):"a1");
+	asm volatile("mret");
+}
+