Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40588 )
Change subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 ......................................................................
soc/intel/tigerlake: Fix FSP SPD index for DDR4
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects.
BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful.
Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/40588/1
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 8664547..d44554a 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -16,6 +16,14 @@ #define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2)))
+/* + * Translate DDR4 channel # to FSP UPD index # for the channel. + * Channel 0 -> Index 0 + * Channel 1 -> Index 4 + * Index 1-3 and 5-7 are unused. + */ +#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) + enum dimm_enable_options { ENABLE_BOTH_DIMMS = 0, DISABLE_DIMM0 = 1, @@ -378,7 +386,7 @@ for (i = 0; i < DDR4_CHANNELS; i++) { ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); + init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); }
/*
Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40588 )
Change subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 ......................................................................
Patch Set 1: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40588 )
Change subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 ......................................................................
Patch Set 1: Code-Review+2
Thanks~
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40588 )
Change subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 ......................................................................
soc/intel/tigerlake: Fix FSP SPD index for DDR4
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects.
BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful.
Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kane Chen kane.chen@intel.com Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 9 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Kane Chen: Looks good to me, approved EricR Lai: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 8664547..d44554a 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -16,6 +16,14 @@ #define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2)))
+/* + * Translate DDR4 channel # to FSP UPD index # for the channel. + * Channel 0 -> Index 0 + * Channel 1 -> Index 4 + * Index 1-3 and 5-7 are unused. + */ +#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) + enum dimm_enable_options { ENABLE_BOTH_DIMMS = 0, DISABLE_DIMM0 = 1, @@ -378,7 +386,7 @@ for (i = 0; i < DDR4_CHANNELS; i++) { ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); + init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); }
/*
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40588 )
Change subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2648 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2647 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2646 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2645
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
EricR Lai (Code Review)
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Furquan Shaikh (Code Review)
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Kane Chen (Code Review)