Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(4 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/6a15abfc_20aea62b PS62, Line 44: one space is enough (applies to all ports)
https://review.coreboot.org/c/coreboot/+/48340/comment/7a44f840_776da340 PS62, Line 47: }" tab (applies to all ports)
https://review.coreboot.org/c/coreboot/+/48340/comment/855f3a70_b7466e50 PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" I know we've gone over this several times. Since we now know that a free-running CLKSRC doesn't use any CLKREQ, how about expressing this as follows?
# Enable PCH PCIE RP 8 using free running CLK 6 # Clock source is shared with LAN and hence marked as free running. register "pch_pcie_rp[PCH_RP(8)]" = "{ .clk_src = 6, .flags = PCIE_RP_CLK_REQ_UNUSED, }"
If a port uses a CLKSRC but does not use any CLKREQ, we can configure the CLKSRC as free-running.
https://review.coreboot.org/c/coreboot/+/48340/comment/5e252cb6_94cde803 PS62, Line 72: .flags = PCIE_RP_CLK_SRC_UNUSED, Does Optane need any CLKSRC?