EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/1
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 428fd4d..38d1c3c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -119,7 +119,12 @@ uint8_t PchHdaIDispCodecDisconnect;
/* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; + struct { + uint8_t enabled, + uint8_t clksrc, + uint8_t clkreq, + } PcieRp[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 7e842a2..7b36e90 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -41,9 +41,13 @@ /* Set CpuRatio to match existing MSR value */ m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
- for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + if (config->PcieRp[i].enabled) + { mask |= (1 << i); + config->PcieClkSrcClkReq[PcieRp[i].clkreq] = PcieRp[i].clksrc; + config->PcieClkSrcUsage[PcieRp[i].clksrc] = i; + } } m_cfg->PcieRpEnableMask = mask;
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/chi... PS1, Line 126: PcieRp make it lowercase ?
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... PS1, Line 48: PcieRp[i].clksrc can u please help me to understand, how this variable will get its value ?
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... PS1, Line 45: if (config->PcieRp[i].enabled) that open brace { should be on the previous line
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 11 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... PS1, Line 48: PcieRp[i].clksrc
can u please help me to understand, how this variable will get its value ?
I hope it can use like this in devicetree. Need to try though... register "PcieRp[6]" = "{ "enabled" = "1", "clksrc" = "3", "clkreq" = "4", }
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/2/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/2/src/soc/intel/alderlake/rom... PS2, Line 48: config->PcieClkSrcUsage[PcieRp[i].clksrc] = i; This may not use for it root port. Need to redefine it.. hmmm..
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 3:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/3/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/3/src/soc/intel/alderlake/rom... PS3, Line 47: config->PcieClkSrcClkReq[config->PcieRp[i].clkreq] = config->PcieRp[i].clksrc; line over 96 characters
https://review.coreboot.org/c/coreboot/+/48340/3/src/soc/intel/alderlake/rom... PS3, Line 48: config->PcieClkSrcUsage[config->PcieRp[i].clksrc] = if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; line over 96 characters
https://review.coreboot.org/c/coreboot/+/48340/3/src/soc/intel/alderlake/rom... PS3, Line 48: config->PcieClkSrcUsage[config->PcieRp[i].clksrc] = if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/48340/3/src/soc/intel/alderlake/rom... PS3, Line 48: config->PcieClkSrcUsage[config->PcieRp[i].clksrc] = if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48340/3/src/soc/intel/alderlake/rom... PS3, Line 48: config->PcieClkSrcUsage[config->PcieRp[i].clksrc] = if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; trailing statements should be on next line
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 4:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/4/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/4/src/soc/intel/alderlake/rom... PS4, Line 47: config->PcieClkSrcClkReq[config->PcieRp[i].clkreq] = trailing whitespace
https://review.coreboot.org/c/coreboot/+/48340/4/src/soc/intel/alderlake/rom... PS4, Line 49: config->PcieClkSrcUsage[config->PcieRp[i].clksrc] = trailing whitespace
https://review.coreboot.org/c/coreboot/+/48340/4/src/soc/intel/alderlake/rom... PS4, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; space prohibited before semicolon
https://review.coreboot.org/c/coreboot/+/48340/4/src/soc/intel/alderlake/rom... PS4, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48340/4/src/soc/intel/alderlake/rom... PS4, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i ; trailing statements should be on next line
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#5).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/5
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/5/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/5/src/soc/intel/alderlake/rom... PS5, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i; space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48340/5/src/soc/intel/alderlake/rom... PS5, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i; trailing statements should be on next line
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#6).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/6
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 6:
I am building crossgcc lol. Let me use the bot to debug
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#7).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 19 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/7
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 7:
@Subrata, this struct is wokred 😊 Do you have ADL_RVP? Or you can find some people to test it if I change the device tree of RVP?
register "PcieRp[6]" = "{ .enabled = 1, .clksrc = 3, .clkreq = 4, }"
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 7:
Adding Meera, if you could verify Eric's CL on ADLRVP with proposed devicetree.cb changes
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#8).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 73 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/8/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/8/src/soc/intel/alderlake/rom... PS8, Line 38: if(config->PcieRp[i].clkreq == 0xff) space required before the open parenthesis '('
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#9).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 73 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/9
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
@All, basically finished the draft version that should work but some troubles need to discuss. For 2. I think just backup the original one is fine.
1. special usage like PCH PCIE RP 8 using free running CLK (0x80). 2. special usage with no RP like: # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" # Enable PCU PCIE PEG Slot 1 and 2 register "PcieClkSrcUsage[3]" = "0x41" register "PcieClkSrcUsage[4]" = "0x42" 3. Just enable the RP without clk assigning. # Enable PCH PCIE RP 11 for optane register "PcieRpEnable[10]" = "1"
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/mainboard/google/brya/v... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/9/src/mainboard/google/brya/v... PS9, Line 5: register "PcieRp[6]" = "{ This is just for testing. Please ignore this :)
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
@Meera, do you have the time to test this?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... PS9, Line 122: struct { In my opinion, all the PCIe related configs below should be combined into a single structure. Probably something like:
enum pcie_rp_flags { PCIE_RP_ENABLED = (1 << 0), PCIE_RP_HOTPLUG_ENABLED = (1 << 1), PCIE_RP_LTR_ENABLED = (1 << 2), PCIE_RP_AER_ENABLED = (1 << 3), PCIE_RP_ALWAYS_ON_CLK = (1 << 4), /* This can be used to set 0x80 for clksrcusage. */ PCIE_RP_LAN_PORT = (1 << 5), /* This can be used to set 0x70 for clksrcusage */ PCIE_RP_CLK_REQ_DETECT = (1 << 6), };
struct pcie_rp_config { uint8_t clk_src; uint8_t clk_req; uint32_t flags; } pcie_rp[CONFIG_MAX_ROOT_PORTS];
and then mainboard can set something like this in devicetree:
pcie_rp_config[0] = { .clk_src = 3, .clk_req = 4, .flags = PCIE_RP_ENABLED | PCIE_RP_LTR_ENABLED | PCIE_RP_AER_ENABLED, };
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 31: /* Back up special usage */ This is not required.
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: PcieClkSrcClkReq You don't need to set this in a local array. It can directly be set in m_cfg->PcieClkSrcClkReq. Same for ClkSrcUsage below.
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq I think this will have to be config->pcie_rp[i].clk_req - 1. Same for clk_src below.
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 43: : i Let's not do this. Instead let's ensure that mainboard sets it correctly.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... PS9, Line 122: struct {
In my opinion, all the PCIe related configs below should be combined into a single structure. […]
BTW, I think we don't need PCIE_RP_ENABLED. Instead, state of PCIe RP in devicetree (on/off) can be used to determine whether it is enabled or not.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... PS9, Line 122: struct {
BTW, I think we don't need PCIE_RP_ENABLED. […]
SG! Let me try this.
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
I think this will have to be config->pcie_rp[i].clk_req - 1. Same for clk_src below.
Why need -1? The schematic is from 0-9, device tree is 0-9 as well.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
Why need -1? The schematic is from 0-9, device tree is 0-9 as well.
What is the FSP UPD expectation? I thought we had to add or subtract one somewhere since the number in schematic and UPD expectations were off by one.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
What is the FSP UPD expectation? I thought we had to add or subtract one somewhere since the number […]
I think you thought is PCIE port in schematic is 1-10 and CLKREQ/CLKSRC is 0-9. But we do subtract RP number in device tree is every project. Do you want keep the RP number same as schematic? Then we can subtract RP-1 here.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
I think you thought is PCIE port in schematic is 1-10 and CLKREQ/CLKSRC is 0-9. […]
Yes, I think it would be better to keep the root port # such that is matches the schematic. You can use 1-X for root port numbers and let 0 be unused or use enums for that as well:
enum pcie_rp { RP_1 = 0, RP_2, RP_3, ... }
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
Yes, I think it would be better to keep the root port # such that is matches the schematic. […]
Let us use enums :p I like this way.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#10).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 95 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/10
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#11).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 96 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/11
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/11/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/11/src/soc/intel/alderlake/ro... PS11, Line 29: continue; trailing whitespace
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#12).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 96 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/12
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 25: 0xFF `PCIE_CLK_NOTUSED`
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 38: 0xff PCIE_CLK_NOTUSED
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#13).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 95 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/13
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 13:
(10 comments)
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/chi... PS9, Line 122: struct {
SG! Let me try this.
Done
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/chi... PS1, Line 126: PcieRp
make it lowercase ?
Done
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... PS1, Line 48: PcieRp[i].clksrc
I hope it can use like this in devicetree. Need to try though... […]
Done
https://review.coreboot.org/c/coreboot/+/48340/2/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/2/src/soc/intel/alderlake/rom... PS2, Line 48: config->PcieClkSrcUsage[PcieRp[i].clksrc] = i;
This may not use for it root port. Need to redefine it.. hmmm..
Ack
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 25: 0xFF
`PCIE_CLK_NOTUSED`
Done
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 31: /* Back up special usage */
This is not required.
Done
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 38: 0xff
PCIE_CLK_NOTUSED
Done
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: config->PcieRp[i].clkreq
Let us use enums :p I like this way.
Done
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 40: PcieClkSrcClkReq
You don't need to set this in a local array. It can directly be set in m_cfg->PcieClkSrcClkReq. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/9/src/soc/intel/alderlake/rom... PS9, Line 43: : i
Let's not do this. Instead let's ensure that mainboard sets it correctly.
Done
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#14).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 95 insertions(+), 52 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/14
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 14:
(13 comments)
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
PS14: I think it would be good to push a separate change for brya since it is adding new code that wasn't present before.
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... PS14, Line 6: nit: one space should be sufficient. same for clk_req below.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 139: uint8_t clk_src; A one-line comment would be helpful here. CLKOUT_PCIE_P/N# used by this root port as per schematics.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 140: clk_req same here: SRCCLKREQ# used by this root port as per schematics.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 148: /* This can be used to set 0x70 for clksrcusage */ : PCIE_RP_LAN_PORT = (1 << 5), I just looked through the UPD description again. This is actually not correct. A PCIE clock source can be assigned to one of the following: 1. PCIe RP 2. LAN port 3. Free running (not used by PCIe or LAN)
For #2, currently, I don't see any ADL board using it. So, we can drop this flag. When we have to support it, we can add a new config: `uint8_t lan_clk;` and that can be used to set 0x70.
About #3, I know Subrata recently added 0x80 for RP8 on adlrvp. I am still not completely convinced it is correct since UPD description says that 0x80 is used for something other than the options stated i.e. other than PCIe RP, LAN, etc. So, I don't understand why it is associated with a RP. Anyways, we can support that case with the PCIE_RP_ALWAYS_ON_CLK for now. But, it would be good if Subrata can confirm if this is really the right configuration. +Subrata.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 152: flags Data type for this should not be enum pcie_rp_flags. flags allows multiple of the enums to be set. I think this should be uint32_t flags;
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; This is not required anymore.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 160: /* PCIe RP L1 substate */ : enum L1_substates_control { : L1_SS_FSP_DEFAULT, : L1_SS_DISABLED, : L1_SS_L1_1, : L1_SS_L1_2, : } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; This should be moved into the above structure.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/fs... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/fs... PS14, Line 266: config->pcie_rp[i].flags & PCIE_RP_LTR_ENABLED ? 1 : 0; I think it would be good to have a helper for the flags:
static bool pcie_is_flag_enabled(const struct pcie_rp_config *pcie_rp, enum pcie_rp_flags flag_mask) { return pcie_rp->flags & flag_mask; }
params->PcieRpLtrEnable[i] = pcie_is_flag_enabled(config->pcie_rp[i], PCIE_RP_LTR_ENABLED); params->PcieRpAdvancedErrorReporting[i] = pcie_is_flag_enabled(config->pcie_rp[i], PCIE_RP_AER_ENABLED); params->PcieRpHotPlug[i] = pcie_is_flag_enabled(config->pcie_rp[i], PCIE_RP_HOTPLUG_ENABLED); ...
struct pcie_rp_config will have to be a named structure in chip.h.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 24: memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, : sizeof(config->PcieClkSrcUsage)); This is not required.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 28: if ((config->pcie_rp[i].flags & PCIE_RP_ENABLED) == 0) Same helper as mentioned in the other file can be used here:
if (!pcie_is_flag_enabled(config->pcie_rp[i], PCIE_RP_ENABLED)) continue;
and so on.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 33: m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] = : config->pcie_rp[i].clk_src; I think the logic is inverted here. UPD description says "Number of ClkReq signal assigned to ClkSrc" which means that the entry provides the ClkReq# and the index is ClkSrc#.
m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_src] = config->pcie_rp[i].clk_req;
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 35: if (config->pcie_rp[i].flags & PCIE_RP_ALWAYS_ON_CLK) : m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src] = 0x80; : else if (config->pcie_rp[i].flags & PCIE_RP_LAN_PORT) : m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src] = 0x70; : else : m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src] = i; Convert to a helper function:
m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src]] = pcie_get_clksrc_usage(config->pcie_rp[i]);
It would be easier to look through the logic behind the selection for clk src usage in a separate helper function of its own.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 14:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
PS14:
I think it would be good to push a separate change for brya since it is adding new code that wasn't […]
This change will remove, I used for verify buildbot:)
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... PS14, Line 6:
nit: one space should be sufficient. same for clk_req below.
Ack
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 160: /* PCIe RP L1 substate */ : enum L1_substates_control { : L1_SS_FSP_DEFAULT, : L1_SS_DISABLED, : L1_SS_L1_1, : L1_SS_L1_2, : } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
This should be moved into the above structure.
okay.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#15).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 119 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/15
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
(9 comments)
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 139: uint8_t clk_src;
A one-line comment would be helpful here. CLKOUT_PCIE_P/N# used by this root port as per schematics.
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 140: clk_req
same here: SRCCLKREQ# used by this root port as per schematics.
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 152: flags
Data type for this should not be enum pcie_rp_flags. flags allows multiple of the enums to be set. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
This is not required anymore.
I kept this for special assigning :
# Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" # Enable PCU PCIE PEG Slot 1 and 2 register "PcieClkSrcUsage[3]" = "0x41" register "PcieClkSrcUsage[4]" = "0x42" I don't know why they need this, any idea to add this into config?
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 160: /* PCIe RP L1 substate */ : enum L1_substates_control { : L1_SS_FSP_DEFAULT, : L1_SS_DISABLED, : L1_SS_L1_1, : L1_SS_L1_2, : } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];
okay.
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/fs... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/fs... PS14, Line 266: config->pcie_rp[i].flags & PCIE_RP_LTR_ENABLED ? 1 : 0;
I think it would be good to have a helper for the flags: […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 24: memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, : sizeof(config->PcieClkSrcUsage));
This is not required.
Need to copy the special usage.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 33: m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] = : config->pcie_rp[i].clk_src;
I think the logic is inverted here. […]
Take Brya for example. SD PCIE_RP8 use REQ_3 for CLKSRC_4, so we should fill PcieClkSrcClkReq[3]=4; And PcieClkSrcUsage[4]=8 right?
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 35: if (config->pcie_rp[i].flags & PCIE_RP_ALWAYS_ON_CLK) : m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src] = 0x80; : else if (config->pcie_rp[i].flags & PCIE_RP_LAN_PORT) : m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src] = 0x70; : else : m_cfg->PcieClkSrcUsage[config->pcie_rp[i].clk_src] = i;
Convert to a helper function: […]
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
I kept this for special assigning : […]
those are for CPU PCIE port. I would recommend not to remove ADLRVP code that much as we are in PO mode still, Also if you need validation support, tag Meera and myself 😊
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
@Subrata and Meera, please try my patch is work or not.. should be fine, hopefully:0
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/14/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
PS14:
This change will remove, I used for verify buildbot:)
Ack.
https://review.coreboot.org/c/coreboot/+/48340/15/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/15/src/mainboard/google/brya/... PS15, Line 5: unrelated change
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
I kept this for special assigning :
Ah, I had missed that adlrvp is already using the PEG port clock mapping as well. We need to enable another config structure for the CPU PCIe ports. The above config can be renamed to pch_pcie_rp and create a similar one for cpu_pcie_rp:
struct pcie_rp_config { uint8_t clk_src; uint8_t clk_req; uint32_t flags; };
struct pcie_rp_config pch_pcie_rp[MAX_PCH_PCIE_ROOT_PORTS]; struct pcie_rp_config cpu_pcie_rp[MAX_CPU_PCIE_ROOT_PORTS];
SoC code will have to handle both these structures:
enum { PCH_PCIE_RP, CPU_PCIE_RP, };
static uint8_t pcie_clk_src_usage(enum pcie_rp_type type, const struct pcie_rp_config *cfg, int rp_number) { if (pcie_is_flag_enabled(cfg, PCIE_RP_ALWAYS_ON_CLK)) return 0x80; if (type == PCH_PCIE_RP) return rp_number; if (type == CPU_PCIE_RP) return 0x40 + rp_number;
die ("Unsupported type!"); }
static uint32_t pcie_rp_init(enum pcie_rp_type type, const struct pcie_rp_config *cfg, size_t cfg_count) { mask = 0;
for (i = 0; i < cfg_count; i++, cfg++) { if (!pcie_is_flag_enabled(cfg, PCIE_RP_ENABLED)) continue; mask |= (1 << i);
if (!pcie_is_flag_enabled(cfg, PCIE_RP_CLK_NOTUSED)) continue;
m_cfg->PcieClkSrcClkReq[cfg->clk_src] = cfg->clk_req; m_cfg->PcieClkSrcUsage[cfg->clk_src] = pcie_clk_src_usage(type, cfg, i); }
return mask; }
m_cfg->PcieRpEnableMask = pcie_rp_init(PCH_PCIE_RP, config->pch_pcie_rp, ARRAY_SIZE(config->pch_pcie_rp)); m_cfg->CpuPcieRpEnableMask = pcie_rp_init(CPU_PCIE_RP, config->cpu_pcie_rp, ARRAY_SIZE(config->cpu_pcie_rp));
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 24: memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, : sizeof(config->PcieClkSrcUsage));
Need to copy the special usage.
See comment on chip.h.
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 33: m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] = : config->pcie_rp[i].clk_src;
Take Brya for example. […]
No, it is the other way around: PcieClkSrcClkReq[4] = 3; PcieClkSrcUsage[4] = 7;
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
I kept this for special assigning : […]
@Furquan, Does PEG port have CLKREQ or just need the src? If it just need src, I think I can separate the init function or add if (type != CPU_PCIE_RP) to guard PcieClkSrcClkReq.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 15:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/15/src/mainboard/google/brya/... File src/mainboard/google/brya/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/15/src/mainboard/google/brya/... PS15, Line 5:
unrelated change
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 148: /* This can be used to set 0x70 for clksrcusage */ : PCIE_RP_LAN_PORT = (1 << 5),
I just looked through the UPD description again. This is actually not correct. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ch... PS14, Line 158: uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
@Furquan, Does PEG port have CLKREQ or just need the src? If it just need src, I think I can separat […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 28: if ((config->pcie_rp[i].flags & PCIE_RP_ENABLED) == 0)
Same helper as mentioned in the other file can be used here: […]
Done
https://review.coreboot.org/c/coreboot/+/48340/14/src/soc/intel/alderlake/ro... PS14, Line 33: m_cfg->PcieClkSrcClkReq[config->pcie_rp[i].clk_req] = : config->pcie_rp[i].clk_src;
No, it is the other way around: […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#16).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 148 insertions(+), 65 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/16
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#17).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 178 insertions(+), 69 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/17
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 17:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 55: PCH_PCIE_RP, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 56: CPU_PCIE_RP, please, no spaces at the start of a line
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 27: die ("Unsupported type!"); space prohibited between function name and open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 62: m_cfg->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; trailing whitespace
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 17:
(6 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 23: RP_1 Probably add PCH_ as a prefix to indicate these are PCH PCIE RP numbers? And we would also need: CPU_RP_1 = 0, CPU_RP_2, ...
BTW, if this enum seems to be growing too long, you can also just use a macro: #define PCIE_RP(x) ((x) - 1) #define PCH_RP(x) PCIE_RP(x) #define CPU_RP(x) PCIE_RP(x)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 39: SRC_1 = (1 << 0), This is not required. You can default initialize all clock sources as disabled and then use pch_pcie_rp and cpu_pcie_rp to initialize the used clocks. See my comment on fsp_params.c
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 54: enum pcie_rp_type { This can be moved to fsp_params.c since it is only used in that file.
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 30: static int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp, : enum pcie_rp_flags flag_mask) : { : return pcie_rp.flags & flag_mask ? 1 : 0; : } This can be added as inline to chip.h so that it can be used by both romstage and ramstage files.
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP Instead of checking PCH_PCIE_RP, should we add a flag, PCIE_RP_NO_CLKREQ and check that? That will help both PCH and CPU root ports.
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 160: disable_unused_clk(m_cfg, config); You can do this before the pcie_rp_init() calls and then you don't need the special PcieClkSrcDisabled config.
i.e.
/* Disable all PCIe clock sources by default. */ for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) m_cfg->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED;
m_cfg->PcieRpEnableMask = pcie_rp_init(..., PCH_PCIE_RP, ...); m_cfg->CpuPcieRpEnableMask = pcie_rp_init(..., CPU_PCIE_RP, ...);
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#18).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 144 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/18
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 18:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 30: static int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp, : enum pcie_rp_flags flag_mask) : { : return pcie_rp.flags & flag_mask ? 1 : 0; : }
This can be added as inline to chip.h so that it can be used by both romstage and ramstage files.
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
Instead of checking PCH_PCIE_RP, should we add a flag, PCIE_RP_NO_CLKREQ and check that? That will h […]
If CPU root ports never wanted CLKREQ, we don't have to add flags for ever CPU root port. Will CPU root port need CLKREQ?
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 160: disable_unused_clk(m_cfg, config);
You can do this before the pcie_rp_init() calls and then you don't need the special PcieClkSrcDisabl […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#19).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 132 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/19
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#20).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 132 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/20
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 23: RP_1
Probably add PCH_ as a prefix to indicate these are PCH PCIE RP numbers? And we would also need: […]
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 39: SRC_1 = (1 << 0),
This is not required. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ch... PS17, Line 54: enum pcie_rp_type {
This can be moved to fsp_params.c since it is only used in that file.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... PS20, Line 361: inline static inline
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
If CPU root ports never wanted CLKREQ, we don't have to add flags for ever CPU root port. […]
Why is that? CPU root ports should be very similar to PCH root ports. Use of CLKREQ depends upon the use case and the device being attached to it. I don't see anything that would prevent a CPU root port from using CLKREQ. Is there something in EDS/PDG that prohibits this?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro... PS20, Line 148: pcie_rp_init nit: I think it would be good to align this one more tab or basically move this to the previous line and anything that overflows the column limit can be moved to this line.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
Why is that? CPU root ports should be very similar to PCH root ports. […]
@Subrata, could you help explain PEG a little bit?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... PS20, Line 361: inline
static inline
Done
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
@Subrata, could you help explain PEG a little bit?
Done
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ro... PS20, Line 148: pcie_rp_init
nit: I think it would be good to align this one more tab or basically move this to the previous line […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#21).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 133 insertions(+), 72 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/21
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#22).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 136 insertions(+), 76 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/22
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... PS22, Line 158: /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ @Subrata, please help check should I keep this logic or not? Or I can just use m_cfg->CpuPcieRpEnableMask = pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS); to replace it.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... PS22, Line 158: /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
@Subrata, please help check should I keep this logic or not? Or I can just use […]
we need to read the CpuPcieRpEnableMask value with and without this CL.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 22:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... PS22, Line 158: /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
we need to read the CpuPcieRpEnableMask value with and without this CL.
My meaning is CpuPcieRpEnableMask depends on SA_DEVFN_CPU_PCIE? The UPD said this is each port per bit. But is_dev_enabled(dev) is only one bit, is this correct??
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 22:
@Subrata, I can't find document for CPU PCIE ports. so far, PEG is represented Graphics. Could you help answer some questions for me? 1. Can this use for another usage? 2. Is it possible CPU PCIE ports overlap PCH ports? If not, maybe we can use flags to combine it. 3. PEG need CLKREQ or not? 4. Does CPU PCIE only depend on pci 06.0? Below description is wrong? Looks like copied from PCIE RP, I don't have ADL FSP to check...
/** Offset 0x0224 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 CpuPcieRpEnableMask;
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 22:
@Meera and Subrata, have you try this on RVP?
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 22:
Patch Set 22:
@Meera and Subrata, have you try this on RVP?
Hi Eric, i'll try this today. Can you please rebase this CL?
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#23).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 137 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/23
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
Patch Set 22:
Patch Set 22:
@Meera and Subrata, have you try this on RVP?
Hi Eric, i'll try this today. Can you please rebase this CL?
Done. BTW,it would be better to dump PCIE config in the FSP log to check the CL work or not :) Thank you!
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
Patch Set 23:
Patch Set 22:
Patch Set 22:
@Meera and Subrata, have you try this on RVP?
Hi Eric, i'll try this today. Can you please rebase this CL?
Done. BTW,it would be better to dump PCIE config in the FSP log to check the CL work or not :) Thank y
Hi Eric, I was able to verify the CL. Please find the PCIe RP Config dump below. ------------------ PCH PCIe RP PreMem Config ------------------ Port[0] RpEnabled= 0 Port[1] RpEnabled= 0 Port[2] RpEnabled= 0 Port[3] RpEnabled= 0 Port[4] RpEnabled= 1 Port[5] RpEnabled= 1 Port[6] RpEnabled= 0 Port[7] RpEnabled= 1 Port[8] RpEnabled= 1 Port[9] RpEnabled= 0 Port[10] RpEnabled= 1 Port[11] RpEnabled= 0 Clock[0] Usage= 40 Clock[0] ClkReq= 0 Clock[1] Usage= 8 Clock[1] ClkReq= 1 Clock[2] Usage= 4 Clock[2] ClkReq= 2 Clock[3] Usage= 41 Clock[3] ClkReq= 3 Clock[4] Usage= 42 Clock[4] ClkReq= 4 Clock[5] Usage= 5 Clock[5] ClkReq= 5 Clock[6] Usage= FF Clock[6] ClkReq= 6 Clock[7] Usage= 80 Clock[7] ClkReq= 6 Clock[8] Usage= FF Clock[8] ClkReq= 8 Clock[9] Usage= FF Clock[9] ClkReq= 9 ClockBuffer= 87
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
@Meera,Thank you. Looks the result is expected. @Furquan, do you want any change of this?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
(5 comments)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ch... PS23, Line 26: pcie_rp_flags A one-line comment for each of these flags would be very helpful.
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ch... PS23, Line 32: PCIE_RP_ALWAYS_ON_CLK nit: For consistency I think it would be better to name these -
/* Clock source is free running i.e. always on. Sets 0x80 for ClkSrcUsage. */ PCIE_RP_CLK_SRC_ALWAYS_ON = /* Clock source is not used by the root port. */ PCIE_RP_CLK_SRC_UNUSED = /* Clock request signal requires probing before enabling CLKREQ# based power management. */ PCIE_RP_CLK_REQ_DETECT = /* Clock request signal is not used by the root port. */ PCIE_RP_CLK_REQ_UNUSED =
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/fs... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/fs... PS23, Line 266: pcie_is_flag_enabled nit: If you add one additional tab before pcie_is_flag_enabled(), it would make it easier to figure that there is an assignment being performed here and in the lines below.
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 150: nit: extra blank line not required
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev) Actually, we can use is_dev_enabled() for all root ports -- PCH and CPU. This will allow us to drop the PCIE_RP_ENABLED flag completely. What do you think?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
Actually, we can use is_dev_enabled() for all root ports -- PCH and CPU. […]
I thought about it, but how to combine with the for loop? PCIE root ports are not continuously... 1c.1-7 then 1d.1-n. And this may slight different in each platform. Or we need another marco for this?
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#24).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 142 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/24
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 23:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ch... PS23, Line 26: pcie_rp_flags
A one-line comment for each of these flags would be very helpful.
I left straight ones;)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ch... PS23, Line 32: PCIE_RP_ALWAYS_ON_CLK
nit: For consistency I think it would be better to name these - […]
Done
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/fs... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/fs... PS23, Line 266: pcie_is_flag_enabled
nit: If you add one additional tab before pcie_is_flag_enabled(), it would make it easier to figure […]
Done
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 150:
nit: extra blank line not required
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
I thought about it, but how to combine with the for loop? PCIE root ports are not continuously... […]
Yeah, I think something like this should work:
#define PCH_DEVFN_PCIE(x) PCH_DEVFN_PCIE##x
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
Yeah, I think something like this should work: […]
Small problem here, this does not work for CPU_PCIE...
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
Small problem here, this does not work for CPU_PCIE...
Yeah, also, the above wouldn't work for PCH RP as well in a loop.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
Yeah, also, the above wouldn't work for PCH RP as well in a loop.
So, I think keep the enable flag is the easy way to go. Any thing need to change?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
So, I think keep the enable flag is the easy way to go. […]
I have an idea in mind to add some helper functions. I can try to push a patch for the helper functions by Friday. Is that okay?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
I have an idea in mind to add some helper functions. […]
SG! ADL is not urgent, this still in early stage. So we have time to improve as we want!
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(2 comments)
devicetree looks much cleaner!! 😎
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 23: pcie_clk_src_usage suggestion: `convert_clk_src_to_fsp`
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 153: !is_dev_enabled(dev) ? 0 : : pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS); suggestion: I think this reads easier inverted, i.e., ``` m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev) ? pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS) : 0; ```
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 24:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 153: !is_dev_enabled(dev) ? 0 : : pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS);
suggestion: I think this reads easier inverted, i.e., […]
I am waiting for Intel answer, still not clear CPU PCIE only relay on this port or not... If not, we can change simply = pie_rp_init...
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#25).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 140 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/25
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 25:
(2 comments)
@Furquan, waiting for your helper 😊
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 23: pcie_clk_src_usage
suggestion: `convert_clk_src_to_fsp`
Done
https://review.coreboot.org/c/coreboot/+/48340/24/src/soc/intel/alderlake/ro... PS24, Line 153: !is_dev_enabled(dev) ? 0 : : pcie_rp_init(m_cfg, CPU_PCIE_RP, config->cpu_pcie_rp, CONFIG_MAX_ROOT_PORTS);
I am waiting for Intel answer, still not clear CPU PCIE only relay on this port or not... […]
Done
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/22/src/soc/intel/alderlake/ro... PS22, Line 158: /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
My meaning is CpuPcieRpEnableMask depends on SA_DEVFN_CPU_PCIE? The UPD said this is each port per b […]
Ack
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 25: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 50: uint32_t flags; nit: mention `enum pcie_rp_flags` in a comment here?
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 160: CONFIG_MAX_ROOT_PORTS I wonder if we should add a new Kconfig for CPU root ports?
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ro... PS25, Line 32: type suggestion: change this word to pcie_rp_type so the error message is a little more informative
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 25:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 160: CONFIG_MAX_ROOT_PORTS
I wonder if we should add a new Kconfig for CPU root ports?
I thought about it. But no information of this... Any Intel kit# mentioned it? To be honest, I don't know much about CPU PCIE ports... can't see in the schematic as well. Brya doesn't use it.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#26).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 141 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/26
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 50: uint32_t flags;
nit: mention `enum pcie_rp_flags` in a comment here?
Done
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 160: CONFIG_MAX_ROOT_PORTS
I thought about it. But no information of this... […]
Ack
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ro... PS25, Line 32: type
suggestion: change this word to pcie_rp_type so the error message is a little more informative
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/25/src/soc/intel/alderlake/ch... PS25, Line 160: CONFIG_MAX_ROOT_PORTS
Ack
TGL only had 4 (TBT) of the CPU-side PCIe RPs; I think ADL has 7 (4 TBT, 2 PCIE gen4, 1 PCIE gen5)? can clean it up later
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
SG! ADL is not urgent, this still in early stage. […]
Sorry about the delay Eric. Holidays and some build duties kept me busy, so I couldn't push this up earlier. Here is what I am thinking: CB:48968, CB:48969.
CB:48968 adds a helper function that returns a mask that can be used to set the FSP UPD directly. CB:48969 is an example of what changes would be required at the SoC level. Since we are dealing with both CPU and PCH root ports, at the SoC level, we will need `get_pch_pcie_rp_table()` and `get_cpu_pcie_rp_table()`. And the same helper function in CB:48968 should work just fine. That will allow us to get rid of PCIE_RP_ENABLED flag completely. It also prevents any inconsistent configuration in devicetree i.e. UPD set to enabled but device set to off, etc.
What do you think?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
Sorry about the delay Eric. […]
Looks good, but same question as before.. Does CPU PCIE only depend on pci 06.0?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
Patch Set 22:
@Subrata, I can't find document for CPU PCIE ports. so far, PEG is represented Graphics. Could you help answer some questions for me?
- Can this use for another usage?
- Is it possible CPU PCIE ports overlap PCH ports? If not, maybe we can use flags to combine it.
- PEG need CLKREQ or not?
- Does CPU PCIE only depend on pci 06.0? Below description is wrong? Looks like copied from PCIE RP, I don't have ADL FSP to check...
/** Offset 0x0224 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 CpuPcieRpEnableMask;
@Subrata, could you help to find person to help answer my question??
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
Looks good, but same question as before.. Does CPU PCIE only depend on pci 06. […]
There is no PCIE 6.x to present more CPU_RP... If you look up the device tree.. still the issue here. But for PCH_RP it's good enough.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
There is no PCIE 6.x to present more CPU_RP... If you look up the device tree.. […]
At least for TGL, the EDS says that the CPU RP 6.0 does not support bifurcation. So, all lanes can be controlled only by controller 6.0. You will have to check the same for ADL to see what controllers exist and what lane configuration is supported.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 26:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/23/src/soc/intel/alderlake/ro... PS23, Line 154: is_dev_enabled(dev)
At least for TGL, the EDS says that the CPU RP 6.0 does not support bifurcation. […]
okay, I think Subrata not answer my question,yet. But I can follow it for review.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#27).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/include/soc/pcie.h A src/soc/intel/alderlake/pcie_rp.c M src/soc/intel/alderlake/romstage/fsp_params.c 8 files changed, 190 insertions(+), 84 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/27
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 27:
Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?
# Enable CPU PCIE RP 1 using PEG CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 0, }" # Enable PCU PCIE PEG Slot 1 and 2 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 3, }" register "cpu_pcie_rp[CPU_RP(3)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 4, }"
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 27:
Patch Set 27:
Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?
# Enable CPU PCIE RP 1 using PEG CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 0, }" # Enable PCU PCIE PEG Slot 1 and 2 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 3, }" register "cpu_pcie_rp[CPU_RP(3)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 4, }"
in the EDS, I see: "The ADL-P processor PCI Express* has two interfaces: • One 8-lane (x8) port supporting PCIE to gen 5.0 or below. • Two 4-lane (x4) port supporting PCIE gen 4.0 or below"
and I read the rest to say that: 00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
also for the PCIE5 port: "Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported"
and for the PCIE4 ports only support 1x4 and 1x4 reversed, so no way to get bifurcation to support x8 on those ports I think.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 27:
Patch Set 27:
Patch Set 27:
Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?
# Enable CPU PCIE RP 1 using PEG CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 0, }" # Enable PCU PCIE PEG Slot 1 and 2 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 3, }" register "cpu_pcie_rp[CPU_RP(3)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 4, }"
in the EDS, I see: "The ADL-P processor PCI Express* has two interfaces: • One 8-lane (x8) port supporting PCIE to gen 5.0 or below. • Two 4-lane (x4) port supporting PCIE gen 4.0 or below"
and I read the rest to say that: 00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
also for the PCIE5 port: "Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported"
and for the PCIE4 ports only support 1x4 and 1x4 reversed, so no way to get bifurcation to support x8 on those ports I think.
@Tim, could you point out to me where has this information? @Furquan, from the information provided by Tim, we may need check 01.0 06.0 06.2 for CPU_RP 1/2/3. If so, it will skip 6.1 may need to change in the cpu_rp check..
@Meera and Subrata, could you help confirm this? But I didn't see adlrvp turn on 00:01.0 and 00:06.2.
00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 28:
(9 comments)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... PS28, Line 22: #define PCIE_RP(x) ((x) - 1) : #define PCH_RP(x) PCIE_RP(x) : #define CPU_RP(x) PCIE_RP(x) : not soc-specific
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... PS28, Line 27: PCIE_RP_HOTPLUG_ENABLED = (1 << 0), : PCIE_RP_LTR_ENABLED = (1 << 1), : /* PCIE RP Advanced Error Report */ : PCIE_RP_AER_ENABLED = (1 << 2), nit: maybe drop _ENABLED? I'd say it's pretty clear what a flag PCIE_RP_HOTPLUG would do
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... PS28, Line 19: t struct pcie_rp_group pch_lp_rp_groups[] = { : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, : { 0 } : }; moving this and the related parts could be done in a separate change to reduce patch size and make review a bit easier
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 34: nit: newline before
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 41: return m_cfg->PcieRpEnableMask not sure if that is a good idea because the function only returns valid results after the fsp mask was written below; what about looking it up directly in the devicetree instead?
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 43: CpuPcieRpEnableMask only one rp?
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 44: die nit: newline before
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 57: pcie_is_flag_enabled(cfg[i], PCIE_RP_CLK_REQ_UNUSED)) : m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; : m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = : convert_clk_src_to_fsp(type, cfg[i], i); this won't be executed when the port is enabled (line 53)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 157: CONFIG_MAX_ROOT_PORTS why pass that als parameter instead of using it in the function?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 28:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 41: return m_cfg->PcieRpEnableMask
not sure if that is a good idea because the function only returns valid results after the fsp mask w […]
This already done by lookup devicetree. It had run m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()) before call this.
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 57: pcie_is_flag_enabled(cfg[i], PCIE_RP_CLK_REQ_UNUSED)) : m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; : m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = : convert_clk_src_to_fsp(type, cfg[i], i);
this won't be executed when the port is enabled (line 53)
oh... I forgot the ! in line53.. thanks.
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 157: CONFIG_MAX_ROOT_PORTS
why pass that als parameter instead of using it in the function?
What do you mean? I think Kconfig if fine.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 28:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 157: CONFIG_MAX_ROOT_PORTS
What do you mean? I think Kconfig if fine.
just use CONFIG_MAX_ROOT_PORTS above in pcie_rp_init:
Instead of this:
static void pcie_rp_init(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type, const struct pcie_rp_config *cfg, size_t cfg_count) { unsigned int i;
for (i = 0; i < cfg_count; i++) {
do this:
static void pcie_rp_init(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type, const struct pcie_rp_config *cfg) { unsigned int i;
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 28:
(6 comments)
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... PS28, Line 22: #define PCIE_RP(x) ((x) - 1) : #define PCH_RP(x) PCIE_RP(x) : #define CPU_RP(x) PCIE_RP(x) :
not soc-specific
Done
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... PS28, Line 27: PCIE_RP_HOTPLUG_ENABLED = (1 << 0), : PCIE_RP_LTR_ENABLED = (1 << 1), : /* PCIE RP Advanced Error Report */ : PCIE_RP_AER_ENABLED = (1 << 2),
nit: maybe drop _ENABLED? I'd say it's pretty clear what a flag PCIE_RP_HOTPLUG would do
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ch... PS28, Line 19: t struct pcie_rp_group pch_lp_rp_groups[] = { : { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, : { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, : { 0 } : };
moving this and the related parts could be done in a separate change to reduce patch size and make r […]
Done
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 41: return m_cfg->PcieRpEnableMask
This already done by lookup devicetree. […]
Done
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 57: pcie_is_flag_enabled(cfg[i], PCIE_RP_CLK_REQ_UNUSED)) : m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; : m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = : convert_clk_src_to_fsp(type, cfg[i], i);
oh... I forgot the ! in line53.. thanks.
Done
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 157: CONFIG_MAX_ROOT_PORTS
just use CONFIG_MAX_ROOT_PORTS above in pcie_rp_init: […]
We plan to add new Kconfig for CPU_RP ports. It would be different size though. Thanks :)
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#29).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 151 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/29
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#31).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 152 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/31
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#32).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 153 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/32
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 32:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/32/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/32/src/soc/intel/alderlake/ro... PS32, Line 20: enum pcie_rp_type { TODO: move to pcie_rp.h
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#33).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 156 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/33
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#34).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 155 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/34
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/34/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/34/src/soc/intel/alderlake/ch... PS34, Line 343: tic inline int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp, : enum pcie_rp_flags flag_mask) : { : return pcie_rp.flags & flag_mask ? 1 : 0; : } : not soc-specific
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/28/src/soc/intel/alderlake/ro... PS28, Line 157: CONFIG_MAX_ROOT_PORTS
We plan to add new Kconfig for CPU_RP ports. It would be different size though. […]
ack
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/34//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48340/34//COMMIT_MSG@9 PS34, Line 9: PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. : Make it easier to just fill the number from schematics. : the change does more than just this
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/34//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48340/34//COMMIT_MSG@9 PS34, Line 9: PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. : Make it easier to just fill the number from schematics. :
the change does more than just this
Will change in the final commit. We still have problem with CPU RP ports need to work out.
https://review.coreboot.org/c/coreboot/+/48340/34/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/34/src/soc/intel/alderlake/ch... PS34, Line 343: tic inline int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp, : enum pcie_rp_flags flag_mask) : { : return pcie_rp.flags & flag_mask ? 1 : 0; : } :
not soc-specific
Yes, will clean up with move pcie_rp_config to pcie_rp.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
Patch Set 27:
Patch Set 27:
Patch Set 27:
Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?
# Enable CPU PCIE RP 1 using PEG CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 0, }" # Enable PCU PCIE PEG Slot 1 and 2 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 3, }" register "cpu_pcie_rp[CPU_RP(3)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 4, }"
in the EDS, I see: "The ADL-P processor PCI Express* has two interfaces: • One 8-lane (x8) port supporting PCIE to gen 5.0 or below. • Two 4-lane (x4) port supporting PCIE gen 4.0 or below"
and I read the rest to say that: 00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
also for the PCIE5 port: "Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported"
and for the PCIE4 ports only support 1x4 and 1x4 reversed, so no way to get bifurcation to support x8 on those ports I think.
@Tim, could you point out to me where has this information? @Furquan, from the information provided by Tim, we may need check 01.0 06.0 06.2 for CPU_RP 1/2/3. If so, it will skip 6.1 may need to change in the cpu_rp check..
@Meera and Subrata, could you help confirm this? But I didn't see adlrvp turn on 00:01.0 and 00:06.2.
00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
sure it's in the processor EDS vol. 1, chapter 7 about PCIe
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
Patch Set 34:
Patch Set 27:
Patch Set 27:
Patch Set 27:
Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?
# Enable CPU PCIE RP 1 using PEG CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 0, }" # Enable PCU PCIE PEG Slot 1 and 2 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 3, }" register "cpu_pcie_rp[CPU_RP(3)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 4, }"
in the EDS, I see: "The ADL-P processor PCI Express* has two interfaces: • One 8-lane (x8) port supporting PCIE to gen 5.0 or below. • Two 4-lane (x4) port supporting PCIE gen 4.0 or below"
and I read the rest to say that: 00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
also for the PCIE5 port: "Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported"
and for the PCIE4 ports only support 1x4 and 1x4 reversed, so no way to get bifurcation to support x8 on those ports I think.
@Tim, could you point out to me where has this information? @Furquan, from the information provided by Tim, we may need check 01.0 06.0 06.2 for CPU_RP 1/2/3. If so, it will skip 6.1 may need to change in the cpu_rp check..
@Meera and Subrata, could you help confirm this? But I didn't see adlrvp turn on 00:01.0 and 00:06.2.
00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
sure it's in the processor EDS vol. 1, chapter 7 about PCIe
Oh, yes... I just read the GPE parts but miss the before.. Looks like your are correct but different series of CPU have different ports. And we don't know the reversal mapping if control by ME or FSP?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
@Furquan, one more thing need to be considered is From Kit#619501, ADL-S PCIE 5.0 port would be swap if lane is reversal. But we don't use it so it's fine. I think we may need another helper function like cpu_rp_enable_mask to deal with CPU ports. Current one can't deal with 06.0 then 06.2 for ADL-P.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
Patch Set 34:
Patch Set 34:
Patch Set 27:
Patch Set 27:
Patch Set 27:
Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?
# Enable CPU PCIE RP 1 using PEG CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 0, }" # Enable PCU PCIE PEG Slot 1 and 2 register "cpu_pcie_rp[CPU_RP(2)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 3, }" register "cpu_pcie_rp[CPU_RP(3)]" = "{ .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_src = 4, }"
in the EDS, I see: "The ADL-P processor PCI Express* has two interfaces: • One 8-lane (x8) port supporting PCIE to gen 5.0 or below. • Two 4-lane (x4) port supporting PCIE gen 4.0 or below"
and I read the rest to say that: 00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
also for the PCIE5 port: "Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported"
and for the PCIE4 ports only support 1x4 and 1x4 reversed, so no way to get bifurcation to support x8 on those ports I think.
@Tim, could you point out to me where has this information? @Furquan, from the information provided by Tim, we may need check 01.0 06.0 06.2 for CPU_RP 1/2/3. If so, it will skip 6.1 may need to change in the cpu_rp check..
@Meera and Subrata, could you help confirm this? But I didn't see adlrvp turn on 00:01.0 and 00:06.2.
00:01.0 (pcie5) has 1 x8 port (pcie5 or lower) 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower) 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)
sure it's in the processor EDS vol. 1, chapter 7 about PCIe
Oh, yes... I just read the GPE parts but miss the before.. Looks like your are correct but different series of CPU have different ports. And we don't know the reversal mapping if control by ME or FSP?
not sure yet, I haven't seen a real FIT kit yet...
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(3 comments)
https://review.coreboot.org/c/coreboot/+/48340/34/src/mainboard/intel/adlrvp... File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/34/src/mainboard/intel/adlrvp... PS34, Line 80: .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_req = 0,
https://review.coreboot.org/c/coreboot/+/48340/34/src/mainboard/intel/adlrvp... PS34, Line 86: .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_req = 3,
https://review.coreboot.org/c/coreboot/+/48340/34/src/mainboard/intel/adlrvp... PS34, Line 90: .flags = PCIE_RP_CLK_REQ_UNUSED, .clk_req = 4,
Attention is currently required from: Furquan Shaikh, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(5 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/24129573_107bea52 PS34, Line 60: .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_CLK_SRC_ALWAYS_ON, What's the purpose of ClkReq if using a free-running ClkSrc?
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/db0099da_11ce0ae3 PS34, Line 264: config->pch_pcie_rp[i] To save some redundancy, I would use a pointer as follows:
for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { const struct pcie_rp_config *const rp_cfg = config->pch_pcie_rp[i];
params->PcieRpL1Substates[i] = get_l1_substate_control(rp_cfg->PcieRpL1Substates);
params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); }
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/5a24ca80_97137cbb PS34, Line 25: cfg nit: pass pointers instead? It should be more efficient than passing by copy
https://review.coreboot.org/c/coreboot/+/48340/comment/f1d89fc2_f7822fd1 PS34, Line 33: + I'd use a bitwise OR here, but it's not a big deal
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/9b9ed101_e4965781 PS34, Line 17: 0x80 This is what the current FSP binaries use, but it could change in the future.
Attention is currently required from: Furquan Shaikh, Angel Pons, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/88bc17cb_26489aaa PS34, Line 17: 0x80
This is what the current FSP binaries use, but it could change in the future.
`PCIE_CLK_FREE` ?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/bd9d6cf8_19aa841d PS34, Line 17: 0x80
`PCIE_CLK_FREE` ?
I don't think it's worth mentioning what the code does (as of now, who knows what could happen in the future). Instead, code should be self-explanatory so that it's easy to figure this out with a quick look at the relevant code.
Attention is currently required from: Furquan Shaikh, Angel Pons, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/a356013c_8a549918 PS34, Line 17: 0x80
I don't think it's worth mentioning what the code does (as of now, who knows what could happen in th […]
Exactly, that's why I like the macro, PCIE_CLK_FREE, it makes the comment unnecessary
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/22dafd34_b9003952 PS34, Line 17: 0x80
Exactly, that's why I like the macro, PCIE_CLK_FREE, it makes the comment unnecessary
okay, make sense.
Attention is currently required from: Furquan Shaikh, Angel Pons, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(5 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/2cafc494_6651a771 PS34, Line 25: convert_ nit: convert_ seems unncessary, clk_src_to_fsp sounds good enough
https://review.coreboot.org/c/coreboot/+/48340/comment/11f6c6c2_359f69c4 PS34, Line 29: 0x80 PCIE_CLK_FREE
https://review.coreboot.org/c/coreboot/+/48340/comment/7544bd14_dae79f56 PS34, Line 44: CpuPcieRpEnableMask This still needs to be mapped to the 3 RPs
https://review.coreboot.org/c/coreboot/+/48340/comment/c22343f7_57535e41 PS34, Line 42: return m_cfg->PcieRpEnableMask & BIT(rp_number); : if (type == CPU_PCIE_RP) : return m_cfg->CpuPcieRpEnableMask; Instead of requiring the user to have written into `m_cfg` before calling this function, why not have this function take a `uint32_t` that is the mask instead?; the caller already knows whether it's CPU or PCH.
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/5cd26afb_b00a7430 PS34, Line 17: 0x80
okay, make sense.
Sorry what I mean is using PCI_CLK_FREE in a devicetree (or code) makes the code easier to read; agree with Angel, leave this comment as `/* Clock source is free running */`.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/99e6abcf_a21cd63e PS34, Line 42: return m_cfg->PcieRpEnableMask & BIT(rp_number); : if (type == CPU_PCIE_RP) : return m_cfg->CpuPcieRpEnableMask;
Instead of requiring the user to have written into `m_cfg` before calling this function, why not hav […]
I think this is work use PcieRpEnableMask/CpuPcieRpEnableMask as parameter and remove the type :) Will try.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 34:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/bf47ba95_135942bb PS34, Line 44: CpuPcieRpEnableMask
This still needs to be mapped to the 3 RPs
Still wait Furquan patch the helper... And I think I need to add new KConfig for CPU_RP count first.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#35).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 146 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/35
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 35:
(4 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/ffd7befa_8afc99a5 PS34, Line 60: .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_CLK_SRC_ALWAYS_ON,
What's the purpose of ClkReq if using a free-running ClkSrc?
I think it is on-chip LAN
https://review.coreboot.org/c/coreboot/+/48340/comment/2d4b0257_251dba9e PS34, Line 80: .flags = PCIE_RP_CLK_REQ_UNUSED,
.clk_req = 0,
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/ffed2f12_20b2d333 PS34, Line 86: .flags = PCIE_RP_CLK_REQ_UNUSED,
.clk_req = 3,
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/2c7e2ba8_f8949066 PS34, Line 90: .flags = PCIE_RP_CLK_REQ_UNUSED,
.clk_req = 4,
Done
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#36).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 144 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/36
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 36:
(10 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48340/comment/28657fbe_9b146f3f PS34, Line 9: PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. : Make it easier to just fill the number from schematics. :
Will change in the final commit. We still have problem with CPU RP ports need to work out.
Done
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/8f0faf3e_85319170 PS34, Line 343: tic inline int pcie_is_flag_enabled(const struct pcie_rp_config pcie_rp, : enum pcie_rp_flags flag_mask) : { : return pcie_rp.flags & flag_mask ? 1 : 0; : } :
Yes, will clean up with move pcie_rp_config to pcie_rp.
Done
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/f735409a_aba08824 PS34, Line 264: config->pch_pcie_rp[i]
To save some redundancy, I would use a pointer as follows: […]
let me think. looks fine.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/b551ee09_491b60cd PS23, Line 154: is_dev_enabled(dev)
okay, I think Subrata not answer my question,yet. But I can follow it for review.
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/1d37fcc6_aafeb0d8 PS28, Line 43: CpuPcieRpEnableMask
only one rp?
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/9ac0a2d7_fdcff608 PS32, Line 20: enum pcie_rp_type {
TODO: move to pcie_rp. […]
only this file use this. no need.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/9ea8c5ce_55035b2a PS34, Line 25: cfg
nit: pass pointers instead? It should be more efficient than passing by copy
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/e2bde202_1c6215db PS34, Line 29: 0x80
PCIE_CLK_FREE
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/c4afa3c6_d5c5c1a4 PS34, Line 42: return m_cfg->PcieRpEnableMask & BIT(rp_number); : if (type == CPU_PCIE_RP) : return m_cfg->CpuPcieRpEnableMask;
I think this is work use PcieRpEnableMask/CpuPcieRpEnableMask as parameter and remove the type :) Wi […]
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/59ad8ec9_44a35c61 PS34, Line 44: CpuPcieRpEnableMask
Still wait Furquan patch the helper... And I think I need to add new KConfig for CPU_RP count first.
Done
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#37).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 137 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/37
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 37:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/5857e60c_fbdbb6f7 PS34, Line 264: config->pch_pcie_rp[i]
let me think. looks fine.
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/1b6cbfca_393a7ded PS34, Line 17: 0x80
Sorry what I mean is using PCI_CLK_FREE in a devicetree (or code) makes the code easier to read; agr […]
Done
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 37:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/d9e067fe_944f49d3 PS37, Line 83: # W/A to FSP issue where FSP is using PCH PCIE port : # enable UPD to download FW on CPU PCIE : register "PchPcieRpEnable[0]" = "1" : register "PchPcieRpEnable[2]" = "1" : register "PchPcieRpEnable[3]" = "1" did we miss this ?
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 37:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/cddf4f17_d3a7897d PS37, Line 83: # W/A to FSP issue where FSP is using PCH PCIE port : # enable UPD to download FW on CPU PCIE : register "PchPcieRpEnable[0]" = "1" : register "PchPcieRpEnable[2]" = "1" : register "PchPcieRpEnable[3]" = "1"
did we miss this ?
no, this patch will based on devicetree to enable it :)
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 37: Code-Review+1
(1 comment)
Patchset:
PS37: LGTM I'll let others keep looking
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 38: Code-Review+2
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#39).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 133 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/39
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#41).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 128 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/41
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 41:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/69dd4f6e_04e4d88c PS41, Line 70: # Enable PCH PCIE RP 11 for optane seems like this not needed.
Attention is currently required from: Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 41:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/999a3109_562de9a3 PS41, Line 70: # Enable PCH PCIE RP 11 for optane
seems like this not needed.
without this hybrid storage won't get detected
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 41:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/97068380_9c7dffa2 PS41, Line 70: # Enable PCH PCIE RP 11 for optane
without this hybrid storage won't get detected
Remember that? We based on device node now. device pci 1d.2 on end # RP11 So RP 11 is enabled when convert to UPD.
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 41:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/9441160c_334dfa9d PS41, Line 70: # Enable PCH PCIE RP 11 for optane
Remember that? We based on device node now. […]
Oh,I think it again, still need here. Since this is no CLK SRC here.
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 41: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48340/comment/a8a2c6b0_84e688b9 PS41, Line 9: Refactor PCIE port config structure. Make it easier to map from schematic. : We don't have to convert the PCIE ports RP number and CLK source in devicetree. : All the convert will be done by SoC level. reflow to 72 chars wide
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#42).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 128 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/42
Attention is currently required from: Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 42: Code-Review+2
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 42:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/48340/comment/6aa5b044_fe46087b PS41, Line 9: Refactor PCIE port config structure. Make it easier to map from schematic. : We don't have to convert the PCIE ports RP number and CLK source in devicetree. : All the convert will be done by SoC level.
reflow to 72 chars wide
Done
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 42: Code-Review+1
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 42:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/040a3fba_60450b78 PS42, Line 274: const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; Shouldn't there be a check here to ensure that the device is enabled? i.e. Get enable mask and skip the configuration if port is disabled?
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/a0c1937e_a2ed8cef PS42, Line 8: #define PCIE_RP(x) ((x) - 1) Add a comment stating that PCIe root port numbers are 1-based, but we use 0-based indexes for the configuration arrays and so this macro subtracts 1 to convert RP# to array index.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 42:
(2 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/7cc65b11_f1bbd1d4 PS42, Line 274: const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
Shouldn't there be a check here to ensure that the device is enabled? i.e. […]
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/a4f74951_b05bb8fe PS42, Line 8: #define PCIE_RP(x) ((x) - 1)
Add a comment stating that PCIe root port numbers are 1-based, but we use 0-based indexes for the co […]
Done
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#43).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 134 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/43
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#44).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 134 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/44
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#45).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 137 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/45
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#46).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 137 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/46
Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 46: Code-Review+2
Attention is currently required from: Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 47: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/68eea993_301f5885 PS47, Line 40: unsigned int nit: `size_t` to match `cfg_count`
Attention is currently required from: Subrata Banik, Michael Niewöhner, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 47:
(7 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/b3f1e757_44dabe91 PS47, Line 47: }" NB. This can also be set inside the respective `device pci` node, now.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/fe8c4f94_339aa69f PS47, Line 34: die("Unsupported pcie_rp_type!"); Nit, it's dead code. Maybe an assert() would be better.
https://review.coreboot.org/c/coreboot/+/48340/comment/2afc9045_43f99002 PS47, Line 48: m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; Why skip the assignment? What is the default value and does it have special meaning?
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/aa223e4d_d5c442a0 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3), I'm a bit confused here. Doesn't this usually mean the clock is used for something else, i.e. not an RP? if not, what's the exact difference to CLK_REQ_UNUSED?
https://review.coreboot.org/c/coreboot/+/48340/comment/3e517882_cae95a99 PS47, Line 25: Nit, needs a line break here to comply to our coding style. Or the alternative block style without dangling asterisks.
https://review.coreboot.org/c/coreboot/+/48340/comment/cd69782b_34b7d4b5 PS47, Line 104: uint32_t flags; Nit, `enum pcie_rp_flags` I assume? That would also make the comment obsolete.
https://review.coreboot.org/c/coreboot/+/48340/comment/316411d4_a1220352 PS47, Line 107: }; Why not keep it together with the flags declaration?
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 47: -Code-Review
(4 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/12194e15_29f250df PS47, Line 47: }"
NB. This can also be set inside the respective `device pci` node, now.
+1. I really like that idea. And hoping that is how we organize things on Google reference board. Makes it easier to read and follow.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/1c2f9831_f5243f25 PS47, Line 42: for (i = 0; i < cfg_count; i++) { nit: This can also be organized to only loop through RPs that are initialized:
while (en_mask) { i = __ffs(en_mask); en_mask &= ~i;
... }
Then you don't need to pass in cfg_count at all. Anyways, not a big deal if we simply loop over the root ports.
https://review.coreboot.org/c/coreboot/+/48340/comment/e2cf0933_f88e0b02 PS47, Line 48: m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
Why skip the assignment? What is the default value and does it have […]
I think it will have to be initialized to 0xFF (PCIE_CLK_NOT_USED) just like PcieClkSrcUsage is on line 142 below.
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/aec6c552_34194f7d PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
I'm a bit confused here. Doesn't this usually mean the clock is used for […]
That is what I am confused about too. I assumed "free running clock" meant that the clock is not associated with any RP, but has some unspecified usage. Hence, it is an attribute of the clock and not of the root port. But, looking at the way it is set up for ADLRVP, it looks like a clock source which has a CLKREQ# associated with it is marked as a free running clock. It seems like a bad workaround for some different issue.
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 47:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/5c3a99e7_4fad9297 PS47, Line 47: }"
+1. I really like that idea. And hoping that is how we organize things on Google reference board. […]
Good idea. @Furquan, would you like to do this?
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 47:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/3e68f88e_c8f0e425 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
That is what I am confused about too. […]
PCIE_RP_CLK_REQ_UNUSED this can remove since CPU_RP have the CLK_REQ... They didn't assign it at first time...
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#48).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 137 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/48
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 48:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/d6fbd1ad_bf203206 PS47, Line 48: m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
I think it will have to be initialized to 0xFF (PCIE_CLK_NOT_USED) just like PcieClkSrcUsage is on l […]
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/611fbe65_5cbc0fd2 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
PCIE_RP_CLK_REQ_UNUSED this can remove since CPU_RP have the CLK_REQ... […]
Done
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 48:
(2 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/6d3c6815_6135faf9 PS47, Line 47: }"
Good idea. […]
I am fine either ways for adlrvp. Maybe Subrata has some preference. For brya, I think it will be good to organize the PCIe related configs under the corresponding RP devices.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/94e5305a_c0bb7f29 PS48, Line 46: continue; I think you still need the check:
if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED))
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 48:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/06f2eff2_86b0e14e PS48, Line 46: continue;
I think you still need the check: […]
oh, any condition of this? If has SRC should have correspond REQ right? I add this only for CPU_RP at first though.
Attention is currently required from: Nico Huber, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 48:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/84f94de7_48242459 PS48, Line 46: continue;
oh, any condition of this? If has SRC should have correspond REQ right? I add this only for CPU_RP a […]
It is not really necessary. A root port can have a CLKSRC and no CLKREQ.
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 48:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/47dbd015_a4e586c6 PS48, Line 46: continue;
It is not really necessary. A root port can have a CLKSRC and no CLKREQ.
oh, okay. I add it back.
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#49).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 140 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/49
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 49:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/ca61410c_05f47aad PS47, Line 47: }"
I am fine either ways for adlrvp. Maybe Subrata has some preference. […]
Let me see how to get devicetree attribute in the romstage.
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 49:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/0b8879a6_4b76eb5c PS47, Line 47: }"
Let me see how to get devicetree attribute in the romstage.
oh, I misunderstood the meaning. You mean put the register under PCI node? like ? device pci 1c.5 on end # RP6 register "pch_pcie_rp[PCH_RP(6)]" = "{ .clk_src = 5, .clk_req = 5, .flags = PCIE_RP_CLK_REQ_DETECT, }"
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 49:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/0d107ddc_31241396 PS47, Line 42: for (i = 0; i < cfg_count; i++) {
nit: This can also be organized to only loop through RPs that are initialized: […]
This would make it very easy for a wrong `en_mask` value to cause an out-of-bounds array access.
Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 49:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/3a80fea6_368cb88c PS47, Line 42: for (i = 0; i < cfg_count; i++) {
This would make it very easy for a wrong `en_mask` value to cause an out-of-bounds array access.
Fair point. en_mask is already ensured to be only # of ports wide long. We can add an additional step before pcie_rp_init to sanitize it if required. en_mask &= ((1 << PORTS_MAX) - 1)
Anyways, I think what we have right now works perfectly fine as well. Also, # of ports isn't super large, so looping over a few extra ports won't hurt.
Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 49:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/d4b8b7e0_1963c14a PS47, Line 47: }"
oh, I misunderstood the meaning. You mean put the register under PCI node? like ? […]
That's right.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 49:
(6 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/1db88705_33ee5b8b PS47, Line 47: }"
That's right.
I did that on brya. I leave here to the Intel. Fair enough?
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/0eaec5b3_a8128d5a PS47, Line 34: die("Unsupported pcie_rp_type!");
Nit, it's dead code. Maybe an assert() would be better.
done
https://review.coreboot.org/c/coreboot/+/48340/comment/97920c9f_19289e7e PS47, Line 40: unsigned int
nit: `size_t` to match `cfg_count`
done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/3197855e_cdf7d651 PS47, Line 25:
Nit, needs a line break here to comply to our coding style. Or the alternative […]
done.
https://review.coreboot.org/c/coreboot/+/48340/comment/0e5fe7f4_913237cf PS47, Line 104: uint32_t flags;
Nit, `enum pcie_rp_flags` I assume? That would also make the comment obsolete.
okay.
https://review.coreboot.org/c/coreboot/+/48340/comment/3baa4926_2f6b2e3f PS47, Line 107: };
Why not keep it together with the flags declaration?
Because I don't want to touch get_l1_substate_control() and change it... This can keep the original structure.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#50).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 139 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/50
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#51).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 139 insertions(+), 88 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/51
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 50:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/d82a2e0f_d00429ff PS47, Line 34: die("Unsupported pcie_rp_type!");
done
Assert not work. In the design, it shouldn't touch the die, so it should be fine. error: control reaches end of non-void function [-Werror=return-type]
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/4de4b757_b0f4545f PS47, Line 34: die("Unsupported pcie_rp_type!");
Assert not work. In the design, it shouldn't touch the die, so it should be fine. […]
Well, assert() is not a drop-in replacement for die(). I'm not sure what should the assertion be checking, though.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 51:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/67f11e0d_dbe84d83 PS47, Line 34: die("Unsupported pcie_rp_type!"); If die() fixes the compiler warning, probably only because it has attribute((noreturn)) or something like that. It's just deferring the construct that turns the warning off. But that's not needed, how about a switch/case with default?
switch (type) { case PCH_PCIE_RP: return rp_number; case CPU_PCIE_RP: default: return 0x40 + rp_number; }
This way you could avoid an `else` path and still have `CPU_PCIE_RP` mentioned explicitly.
I only stumbled over this because people seem to be concerned about code sizes lately. The die() statement probably adds 40B of nothing.
Well, assert() is not a drop-in replacement for die(). I'm not sure what should the assertion be checking, though.
The assertion would be:
assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP);
Assertions are mere documentation (unless you have static code analyzation check them), so doesn't change anything about the compiler warning. It is also redundant because we already specify type constraints. Alas, those are not enforced in C :-/
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/9b3d82ae_4bc9ee99 PS47, Line 107: };
Because I don't want to touch get_l1_substate_control() and change it... […]
What I meant is that we have now the flags declaration for board config on top, then a bunch of unrelated function prototypes and then board configuration again. I'm also wondering why these things are mixed in a single header file (IIRC, I already commented elsewhere about that).
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/482f8d64_3e4d46f6 PS47, Line 34: die("Unsupported pcie_rp_type!");
If die() fixes the compiler warning, probably only because it has attribute((noreturn)) […]
let me try this
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 51:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/991d28d7_06642365 PS47, Line 107: };
What I meant is that we have now the flags declaration for board config […]
Oh,do you mean move it up? Will do clean up here. We want to put the FSP common things together and keep it simple for further developer. This is why we are trying to do.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#52).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 147 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/52
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 52:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/4057cd49_57468c30 PS47, Line 34: die("Unsupported pcie_rp_type!");
let me try this
I think I can just move assert above the if statement..
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#53).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 148 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/53
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 53:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/04ad8e4c_228807cf PS47, Line 34: die("Unsupported pcie_rp_type!");
I think I can just move assert above the if statement..
okay, we put the assert before the if statement, so we can make sure the type is what we want. In this case we can use if..else then switch case.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#54).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 148 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/54
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 54: Code-Review+1
(3 comments)
Patchset:
PS54: Change looks okay to me. It would be good if Subrata/Meera can provide some clarification on the "free running" clock configuration.
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/082cf9db_b1ccebbd PS47, Line 47: }"
I did that on brya. I leave here to the Intel. […]
SGTM
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/332e0b20_cd0558a9 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Done
But, it is still not clear.
Configuration 1: For a root port, a clock source would be always on and there is no CLKREQ# associated with it. This is determined by PCIE_RP_CLK_REQ_UNUSED.
Configuration 2: For a root port, a clock source provided by the SoC is not used. This is determined by PCIE_RP_CLK_SRC_UNUSED.
Configuration 3: For a root port, a clock source is assigned, but it is considered as "free running", which I think means clock source would be always on and there is no CLKREQ# associated with it. So how is this different than configuration 1 above?
Subrata/Meera - any inputs on this?
Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 55: Code-Review+1
(1 comment)
Patchset:
PS55: will wait for info about clk
Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Subrata Banik, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#56).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 148 insertions(+), 96 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/56
Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS56: @Meera, could you help verify this as well.
Attention is currently required from: Nico Huber, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS56: @Subrata, would you like to answer Furquan's question?
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS54:
Change looks okay to me. […]
This is specific to ADLRVP, I would say, i heard that new RVP already fix that issue, let me try something quickly to avoid confusion of free running
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS56:
@Meera, could you help verify this as well.
Hi Eric, I verified this as well yesterday along with Furquan's patch train :) Sorry, forgot to update here. Works fine.
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS56: @Furquan, do you want to raise an issue for free running clock? Then we can go ahead, this block the brya bring up as well.
Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(2 comments)
Patchset:
PS54:
This is specific to ADLRVP, I would say, i heard that new RVP already fix that issue, let me try som […]
Subrata, were you able to figure this out? Do you have more information to share here?
Patchset:
PS56:
@Furquan, do you want to raise an issue for free running clock? Then we can go ahead, this block the […]
Sure, let's see if we can get some information from Subrata today. If not, I can raise a separate bug for this.
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS54:
Subrata, were you able to figure this out? Do you have more information to share here?
Yes Furquan, i will setup new RVP tomorrow and let you know how things are now
Attention is currently required from: Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/b6946ab6_162c20e1 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
But, it is still not clear. […]
This looks still unaswered.
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/47e9bbcf_5749c89f PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
This looks still unaswered.
Let's wait Subrata for update.
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/9bf1e9f6_5095c656 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Let's wait Subrata for update.
Looks like in order to use x1 DT slot (RP8) at PCH side, we need to make sure CLKSRC -> 7 and CLKREQ -> 6. As CLKREQ 6 is used for both PCH LAN and RP8 hence we need to make it as free running clock rather assign to particular RP as other PCIe CLK does
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56: Code-Review+2
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/def44fe9_7dca2e6f PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Looks like in order to use x1 DT slot (RP8) at PCH side, we need to make sure CLKSRC -> 7 and CLKREQ […]
@Subrata,Thanks. Any other usage of "free running clock" rather than on-board LAN? In my experience this always request by LAN chip.
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/c2d6c898_7a381ed3 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
@Subrata,Thanks. […]
not really for LAN always, in this design we need to only use free running for clkreq 6
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
Patchset:
PS54:
Yes Furquan, i will setup new RVP tomorrow and let you know how things are now
Ack
Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/13516ea9_2e4ebaec PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
As CLKREQ 6 is used for both PCH LAN and RP8 hence we need to make it as free running clock rather assign to particular RP as other PCIe CLK does
Wait.. did you mean CLKSRC7 is used for both PCH LAN and RP8? I don't understand the intent behind sharing of CLKREQ for PCH LAN and RP8.
Also, what is the advantage of setting CLKREQ for the free running clock source? I think that is incorrect.
Eric - I think what we need to do here is: a. Remove the enum PCIE_RP_CLK_FREE since it is not really associated with the root port. b. Add another config field for pcie_clk_config[CONFIG_MAX_PCIE_CLOCKS]; and define a separate enum: ``` enum pcie_clk_src_flags { PCIE_CLOCK_FREE_RUNNING, } ```
With this, mainboard can provide all RP related configuration by using `pcie_rp_config` and any special clock related configuration using `pcie_clk_config`.
With this, `soc_memory_init_params()` will have to do something like:
``` for (i = 0; i < CONFIG_MAX_PCIE_CLOCKS; i++) { if (pcie_clk_config[i].flags & PCIE_CLOCK_FREE_RUNNING) m_cfg->PcieClkSrcUsage[i] = PCIE_CLK_FREE_RUNNING; else m_cfg->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; m_cfg->PcieClkSrcClkReq[i] = PCIE_CLK_NOTUSED; } ```
and in adlrvp, it can then use: ``` # Enable PCH PCIE RP 8 using free running CLK (0x80) register "pch_pcie_rp[PCH_RP(8)]" = "{ /* Clock source is shared with LAN and hence marked as free running. */ .flags = PCIE_RP_CLK_SRC_UNUSED, }" register "pcie_clk_config[7].flags" = "PCIE_CLOCK_FREE_RUNNING" ```
Does that make sense?
Attention is currently required from: Nico Huber, Furquan Shaikh, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/e63a91a5_6a351ef5 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
As CLKREQ 6 is used for both PCH LAN and RP8 hence we need to make it as free running clock rather assign to particular RP as other PCIe CLK does
Wait.. did you mean CLKSRC7 is used for both PCH LAN and RP8? I don't understand the intent behind sharing of CLKREQ for PCH LAN and RP8.
For RP8 CLKSRC is 7 and CLKREQ is 6 which is muxed between LAN and RP8
Also, what is the advantage of setting CLKREQ for the free running clock source?
Device on PCH DT slot won't work if we don't configure the CLKREQ accordingly
Attention is currently required from: Nico Huber, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/fd2c6934_2b0d25a8 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Also, what is the advantage of setting CLKREQ for the free running clock source?
Device on PCH DT slot won't work if we don't configure the CLKREQ accordingly
Sorry, don't mean to keep dragging this discussion. But, I don't understand what role CLKREQ plays if the CLKSRC is always on? Or am I misunderstanding the term "free running clock"?
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/3d9e7107_ee8d9207 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Also, what is the advantage of setting CLKREQ for the free running clock source? […]
Maybe not running with specific speed/frequency?
Attention is currently required from: Nico Huber, Furquan Shaikh, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/34906c70_20aa02d2 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Maybe not running with specific speed/frequency?
@Subrata, what we want to figure out is if CLKSRC is free running still bond to RP and CLKREQ no matter use mux or not. At least, when I developed NB in windows, there always have CLKREQ bond to the CLKSRC or the LAN would not work.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/ab26d3e5_8a575a82 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
@Subrata, what we want to figure out is if CLKSRC is free running still bond to RP and CLKREQ no mat […]
Hmmm... If a CLKSRC is used but doesn't have an associated CLKREQ pin, I think it *must* be free-running.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/401cb03b_a4bd79e2 PS56, Line 58: clk_src = 7, https://review.coreboot.org/c/coreboot/+/49981 please take a look
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/4fb12a8f_3970bdf7 PS56, Line 58: clk_src = 7,
okay, but this still not answer the free running CLK question. I think we need the definition of "what free running CLK is", free mean without CLKREQ or something else?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/438c3c39_53ccb12a PS56, Line 58: clk_src = 7,
"what free running CLK is", free mean without CLKREQ or something else?
CLKSRC is not mapped to any port and clock will be keep on running, eventually allow PCIe device to work properly but downside is power consumption.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/c9c53fe3_8f2cb8aa PS56, Line 58: clk_src = 7,
"what free running CLK is", free mean without CLKREQ or something else? […]
Why would a free-running CLKSRC use a CLKREQ signal?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/1a859751_d80450bd PS56, Line 58: clk_src = 7,
Why would a free-running CLKSRC use a CLKREQ signal?
Subrata explained that, they share the same CLKSRC for LAN and SD card. LAN is not require CLKREQ but SD card need? @Subrata, is my understanding correct? So I will patch for what Furquan mentioned.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 56:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/ae451711_1ac43076 PS56, Line 58: clk_src = 7,
Subrata explained that, they share the same CLKSRC for LAN and SD card. […]
Angel is right here, https://review.coreboot.org/c/coreboot/+/49981 updated the patchset, we don't need CLKREQ for free running CLKSRC
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#57).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 151 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/57
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 57:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/0f668c71_b4ea2356 PS57, Line 58: /* # please 😊
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#58).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 151 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/58
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#59).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 151 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/59
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 59:
(3 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/ea78d453_a10c519e PS56, Line 58: clk_src = 7,
Angel is right here, https://review.coreboot. […]
Done
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/3c229fd9_3e9b679d PS57, Line 58: /*
# please 😊
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/48925c36_13857636 PS47, Line 22: PCIE_RP_CLK_FREE = (1 << 3),
Hmmm... […]
Done
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 59: Code-Review+1
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/a89e34ab_050ad492 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running. .clk_src = 6, is not required now ?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#60).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 5 files changed, 151 insertions(+), 94 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/60
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 59:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/c3627b19_b7538af7 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
.clk_src = 6, is not required now ?
yes, not required. the clk_src is help mapping CLKSRC to the RP. But free running CLK is RP irrelevant. I think below should change to 6.. Could you help verify next patch to see SD card working or not?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 60:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/db2add7e_aae50196 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
yes, not required. the clk_src is help mapping CLKSRC to the RP. […]
latest patchset u mean ?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 60:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/690ed9b5_fd6f6838 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
latest patchset u mean ?
patch60 should worked :p
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 60: Code-Review+1
(3 comments)
Patchset:
PS60: Thanks for your patience Eric. Just one comment about the usage of PCIE_CLK_FREE. I think it is defined as enum and macro. But there are really two different values in the two cases. I think we can just drop pch.h completely and move the definitions to romstage/fsp_params.c since they are now used only in that file. Also, better to add the prefix FSP_ to indicate that they are the values expected by FSP.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/a492e319_2cd855be PS60, Line 142: PCIE_CLK_FREE Looks like PCIE_CLK_FREE got reused for two different purposes.
1. Mainboard setting in pcie_clk_config_flag --> I think this should be named PCIE_CLK_FREE_RUNNING
2. FSP value for free running clock --> I think it should be named FSP_CLK_FREE_RUNNING just to make it clear that it is something that FSP expects. It will be the one that is assigned to PcieClkSrcUsage.
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/3943f43e_f7de421b PS60, Line 33: PCIE_CLK_FREE Woops. This name clashes with the definition her required by FSP: https://review.coreboot.org/cgit/coreboot.git/tree/src/soc/intel/alderlake/i...
Probably name this PCIE_CLK_FREE_RUNNING?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 60:
(2 comments)
Patchset:
PS60:
Thanks for your patience Eric. Just one comment about the usage of PCIE_CLK_FREE. […]
SG!! Let me try.
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/2c2cd69c_fefbdf27 PS60, Line 33: PCIE_CLK_FREE
Woops. This name clashes with the definition her required by FSP: https://review.coreboot. […]
Oh, I think we should deal with LAN 0x70 as well?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 60:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/aa21400b_645f3a51 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
latest patchset u mean ?
Unable to detect PCIe based SD card with latest code
localhost ~ # dmesg | grep mmc
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#61).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c D src/soc/intel/alderlake/include/soc/pch.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/uart.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 9 files changed, 158 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/61
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 61:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/b11f1068_7a317394 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Unable to detect PCIe based SD card with latest code […]
maybe dump the PCIE config from FSP to debug a little bit?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 61:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/15210966_fb22d95e PS60, Line 142: PCIE_CLK_FREE
Looks like PCIE_CLK_FREE got reused for two different purposes. […]
Done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/50eb79f9_dbd9d35a PS60, Line 33: PCIE_CLK_FREE
Oh, I think we should deal with LAN 0x70 as well?
Done
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 61:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/7ad2d494_ff50dfea PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
maybe dump the PCIE config from FSP to debug a little bit?
I think it is because of https://review.coreboot.org/c/coreboot/+/48340/comment/a492e319_2cd855be/. PCIE_CLK_FREE value was being set incorrectly.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 61: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/0f91bfe9_d4db6385 PS61, Line 20: PCIE FSP here too?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 61:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/9ea37a68_d9b4dde0 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
I think it is because of https://review.coreboot.org/c/coreboot/+/48340/comment/a492e319_2cd855be/. […]
Without Eric's CL
Clock[6] Usage= 80 Clock[6] ClkReq= 0
Status: Device Detected
with Eric' CL
Clock[6] Usage= 7 Clock[6] ClkReq= 0
Status: Device Not Detected
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#62).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c D src/soc/intel/alderlake/include/soc/pch.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/uart.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 9 files changed, 158 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/62
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 61:
(2 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/e40e9fcb_b09a7263 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Without Eric's CL […]
I think it's fixed now.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/4ad36597_1671e13c PS61, Line 20: PCIE
FSP here too?
fine :)
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62: Code-Review+1
(1 comment)
Patchset:
PS62: LGTM. Waiting for validation by Subrata.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/2a97b53d_bf7f8583 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
I think it's fixed now.
Your log, seems like the old code base. Maybe clean up then build again :(
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/127922f5_fb12cf0e PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Your log, seems like the old code base. […]
Device is still not working on RP8
Clock[6] Usage= 80 Clock[6] ClkReq= FF
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/d87a6a0e_2156d1bf PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Device is still not working on RP8 […]
CLKREQ can't be FF? Any other different config on this?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/6a180268_2586aa07 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
CLKREQ can't be FF? Any other different config on this?
Clock[6] Usage= 80 Clock[6] ClkReq= FF
This is what we expected. Could you help find other setting might impact this?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/ce80e913_f15de594 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
CLKREQ can't be FF? Any other different config on this?
others are good
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/4b334144_d7c3a4fd PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
others are good
PcieClkSrcClkReq should keep 0 as default? Please help try remove m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; see it works or not.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(4 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/6a15abfc_20aea62b PS62, Line 44: one space is enough (applies to all ports)
https://review.coreboot.org/c/coreboot/+/48340/comment/7a44f840_776da340 PS62, Line 47: }" tab (applies to all ports)
https://review.coreboot.org/c/coreboot/+/48340/comment/855f3a70_b7466e50 PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" I know we've gone over this several times. Since we now know that a free-running CLKSRC doesn't use any CLKREQ, how about expressing this as follows?
# Enable PCH PCIE RP 8 using free running CLK 6 # Clock source is shared with LAN and hence marked as free running. register "pch_pcie_rp[PCH_RP(8)]" = "{ .clk_src = 6, .flags = PCIE_RP_CLK_REQ_UNUSED, }"
If a port uses a CLKSRC but does not use any CLKREQ, we can configure the CLKSRC as free-running.
https://review.coreboot.org/c/coreboot/+/48340/comment/5e252cb6_94cde803 PS62, Line 72: .flags = PCIE_RP_CLK_SRC_UNUSED, Does Optane need any CLKSRC?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/81d1e837_e9e88a92 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
others are good
--- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -83,13 +83,11 @@ chip soc/intel/alderlake
# Enable CPU PCIE RP 2 using CLK 3 register "cpu_pcie_rp[CPU_RP(2)]" = "{ x .clk_req = 3, .clk_src = 3, }"
# Enable CPU PCIE RP 3 using CLK 4 register "cpu_pcie_rp[CPU_RP(3)]" = "{ x .clk_req = 4, .clk_src = 4, }"
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 0469f49..1b9ef9b 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -148,7 +148,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; else m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; x m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; + m_cfg->PcieClkSrcClkReq[i] = 0; }
i have made this changes to align the UPDs bt still, Device on x4 slot is not getting detected. Need to debug looks like
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(3 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/785b0611_2f4595ec PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
--- a/src/mainboard/intel/adlrvp/devicetree.cb […]
You means CPU PCIE not work as well? Can this fix the SD card port? Could PCIE_RP_CLK_REQ_DETECT effect the CLK? Do we need this for the port have REQ?
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/17c406cc_43c11241 PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
I know we've gone over this several times. […]
Not only free running, we still have LAN as 0x70. Extra flag can help reduce the complexity
https://review.coreboot.org/c/coreboot/+/48340/comment/a5e1aed6_02797d36 PS62, Line 72: .flags = PCIE_RP_CLK_SRC_UNUSED,
Does Optane need any CLKSRC?
This is share with SSD. This is co-layout for SSD and Optane. Since SSD is 4 lane optane is 2 lane.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/f187f0ed_d2338f4b PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
You means CPU PCIE not work as well? Can this fix the SD card port? Could PCIE_RP_CLK_REQ_DETECT eff […]
Device at CPU RP 2 and 3 are not getting detected along with PCH DT x4 slot. I don't know the exact root cause, i was trying to make sure that UPD values are align bt still see PCH x4 slot is not working, need to debug further.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/d0081876_1eadac74 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Device at CPU RP 2 and 3 are not getting detected along with PCH DT x4 slot. […]
okay, looks this can't be resolved quickly. I'll tweak the bray to the old way. And patch it after here is done. Keep me post if any finding :)
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/ca79062f_fecc7252 PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
Since we now know that a free-running CLKSRC doesn't use any CLKREQ, how about expressing this as follows?
I think the "free-running clock source" is basically useful for cases where it is not associated with any PCIe root port or used in some non-default configuration (e.g. PCIe multiplexers). In such cases, the clock source is marked as 0x80 instead of configuring it for a particular root port. Hence, I think it is important to allow the mainboard to configure the clock source without having to associate it with any root port. Same goes for CLK for LAN.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 62:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/68c0205a_537a3eb4 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
okay, looks this can't be resolved quickly. I'll tweak the bray to the old way. […]
Subrata, can you please provide the dump of PCIe related UPDs: 1. in working case 2. with this CL
I think we should start there to see what the differences are.
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#63).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c D src/soc/intel/alderlake/include/soc/pch.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/uart.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 10 files changed, 210 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/63
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 63:
(3 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/bcdc27b6_65b5c5c1 PS62, Line 44:
one space is enough (applies to all ports)
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/2984d2c8_9d56e39d PS62, Line 47: }"
tab (applies to all ports)
Done
https://review.coreboot.org/c/coreboot/+/48340/comment/bfc054ae_a3aa46ea PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
Since we now know that a free-running CLKSRC doesn't use any CLKREQ, how about expressing this as […]
Echo to Furquan.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. Subrata Banik has uploaded a new patch set (#64) to the change originally created by EricR Lai. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 113 insertions(+), 86 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/64
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 64:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/d6599ec3_6ab32362 PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Subrata, can you please provide the dump of PCIe related UPDs: […]
Verified all PCIE devices are working with this patch trend
----------------- PCH PCIe RP PreMem Config ------------------ Port[0] RpEnabled= 1 Port[1] RpEnabled= 0 Port[2] RpEnabled= 1 Port[3] RpEnabled= 1 Port[4] RpEnabled= 1 Port[5] RpEnabled= 1 Port[6] RpEnabled= 0 Port[7] RpEnabled= 1 Port[8] RpEnabled= 1 Port[9] RpEnabled= 0 Port[10] RpEnabled= 1 Port[11] RpEnabled= 0 Clock[0] Usage= 40 Clock[0] ClkReq= 0 Clock[1] Usage= 8 Clock[1] ClkReq= 1 Clock[2] Usage= 4 Clock[2] ClkReq= 2 Clock[3] Usage= 41 Clock[3] ClkReq= 3 Clock[4] Usage= 42 Clock[4] ClkReq= 4 Clock[5] Usage= 5 Clock[5] ClkReq= 5 Clock[6] Usage= 80 Clock[6] ClkReq= FF Clock[7] Usage= 0 Clock[7] ClkReq= FF Clock[8] Usage= 0 Clock[8] ClkReq= FF Clock[9] Usage= 0 Clock[9] ClkReq= FF
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has uploaded a new patch set (#65) to the change originally created by EricR Lai. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 113 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/65
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(2 comments)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/ae177008_17bc71fa PS65, Line 149: pcie_clk_config_flag PCIE_RP_CLK_SRC_UNUSED is set as part of root port config and not clock config.
https://review.coreboot.org/c/coreboot/+/48340/comment/f3f3715d_b1073b45 PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */ How can FSP/coreboot disable SRC CLK from an external clock chip?
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/618defeb_52a68d2e PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Verified all PCIE devices are working with this patch trend […]
Good news!
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/e5b6f153_5b2c8676 PS65, Line 149: pcie_clk_config_flag
PCIE_RP_CLK_SRC_UNUSED is set as part of root port config and not clock config.
Why we need extra config here? If ADL-P need set PcieClkSrcUsage[i] = 0 as default, you can switch the case and just use else.. after else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/cc4878d0_d731f0f4 PS65, Line 152: else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) I think we should make a method to treat the external clock instead of the CONFIG based on your comment in CB:50130 .
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
Patchset:
PS65: @Subrata, could you elaborate the expect PCIE CLK setting for FSP? Can we disable all by default? Or need to enable by default etc... Then we can come up a good way to dealt with it.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
Patchset:
PS65:
@Subrata, could you elaborate the expect PCIE CLK setting for FSP? Can we disable all by default? Or […]
I need little time Eric, things are not exact match when i'm reading spec and FSP code. As per FSP, SoC has access to 10 CLKSRC hence FSP can disable those CLKSRC and thats what i'm seeing when CLKSRC[8] is getting disable, i'm seeing x4 port is not working. Need to understand it better
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
Patchset:
PS65:
I need little time Eric, things are not exact match when i'm reading spec and FSP code. […]
sure, it's worth to wait for the better design. And please help consider the later CPU might be. I hope this can apply to all SOC in a good shape :)
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 65:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/1f84ed63_060784cc PS65, Line 152: else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
I think we should make a method to treat the external clock instead of the CONFIG based on your comm […]
I just wrote a comment on CB:50130 . As far as I understand it, we simply need to consider that multiple RPs can share the same CLKSRC while still having different CLKREQs.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Subrata Banik has uploaded a new patch set (#66) to the change originally created by EricR Lai. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 110 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/66
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 66:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/2d8da989_d2734f76 PS65, Line 152: else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
I just wrote a comment on CB:50130 . […]
How would be different RP use the same CLKSRC describe in the FSP? Always the 0x80? Assign different CLKREQ for same CLKSRC is okay but CLKSRC only can apply to one RP expect 0x70 and 0x80. And we can separate CONFIG_MAX_PCIE_CLOCKS_SRC and CONFIG_MAX_PCIE_CLOCKS_REQS.. if they may not equal. @Subrata, I think you can add in CB:50130
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 66:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/4b69147a_fba21c25 PS66, Line 123: uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCKS]; This only can apply to 7 due to real src is 7. And change to pcie_clk_src_flag.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 66:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/312d52ad_ace26f65 PS65, Line 152: else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
How would be different RP use the same CLKSRC describe in the FSP? Always the 0x80? Assign different […]
Good question. I have no idea how to express that in FSP UPDs.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner, EricR Lai. Subrata Banik has uploaded a new patch set (#67) to the change originally created by EricR Lai. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 110 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/67
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Subrata Banik has uploaded a new patch set (#68) to the change originally created by EricR Lai. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 110 insertions(+), 90 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/68
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 68:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/d8b00ee6_c944d748 PS68, Line 151: m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; Use another for loop for REQ. And if this worked on RVP, all things should be fine so far.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Subrata Banik has uploaded a new patch set (#69) to the change originally created by EricR Lai. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 110 insertions(+), 87 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/69
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 69:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/1d21d5fa_fbd6c99a PS68, Line 151: m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
Use another for loop for REQ. And if this worked on RVP, all things should be fine so far.
https://review.coreboot.org/c/coreboot/+/50162
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 69:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/33cb8889_d2cef9e5 PS68, Line 151: m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED;
LGTM. Let wait others review :) Thanks for the working. Hopefully we can apply this on next platform.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#70).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 148 insertions(+), 126 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/70
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70:
(5 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/1a02270d_0239ddd7 PS62, Line 58: register "pch_pcie_rp[PCH_RP(8)]" = "{ : .flags = PCIE_RP_CLK_SRC_UNUSED, : }" : register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
Echo to Furquan.
Done
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/63fd55b2_3d588ca2 PS66, Line 123: uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCKS];
This only can apply to 7 due to real src is 7. And change to pcie_clk_src_flag.
Done
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/419d5e60_1ba7f676 PS65, Line 149: pcie_clk_config_flag
Why we need extra config here? If ADL-P need set PcieClkSrcUsage[i] = 0 as default, you can switch t […]
Ack
https://review.coreboot.org/c/coreboot/+/48340/comment/1ae600b4_3d166e7e PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
How can FSP/coreboot disable SRC CLK from an external clock chip?
Maybe external CLK chip is control by GPIO maybe? Or it always running.
https://review.coreboot.org/c/coreboot/+/48340/comment/297fd399_be2cfbdb PS65, Line 152: else if (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_M))
Good question. I have no idea how to express that in FSP UPDs.
Ack
Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70: Code-Review+1
(2 comments)
Patchset:
PS70: Change looks okay. Waiting for reviews from others on the CL.
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/981dbf15_80279692 PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
Maybe external CLK chip is control by GPIO maybe? Or it always running.
But, FSP has no knowledge of the external chip. The UPDs here are specifically for the clocks that are under the control of SoC.
Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/5dc4aaac_1c89b62e PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
But, FSP has no knowledge of the external chip. […]
Good point! We will use the external clock in zork. I think it will always running and turn on/off with some system power.
Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70: Code-Review+1
Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70: Code-Review+2
(2 comments)
Patchset:
PS70: Looks great Eric!
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/90e30cee_03989eb8 PS70, Line 29: uint32_t flags, unused
Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 70:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/1a365ff8_a2e349c8 PS70, Line 29: uint32_t flags,
unused
Nice catch!
Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner. Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#71).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 150 insertions(+), 126 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/71
Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 71:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/51935305_cafd1d01 PS65, Line 151: /* Don't disable SRC CLK from external clock chip on ADL-P */
Good point! We will use the external clock in zork. […]
Ack
Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Michael Niewöhner, EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 71: Code-Review+2
(1 comment)
Patchset:
PS71: these long patchsets can get draining, thanks for your patience! 🎉
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 5 files changed, 150 insertions(+), 126 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index 51a39c0..647ea42 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -14,42 +14,13 @@ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
- # Enable WLAN PCIE 5 using clk 2 - register "PchPcieRpEnable[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieClkSrcUsage[2]" = "5" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieRpAdvancedErrorReporting[5]" = "1" - - # Enable WWAN PCIE 6 using clk 5 - register "PchPcieRpEnable[6]" = "1" - register "PcieRpLtrEnable[6]" = "1" - register "PcieClkSrcUsage[5]" = "6" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieRpAdvancedErrorReporting[6]" = "1" - - # Enable SD Card PCIE 8 using clk 3 - register "PchPcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieRpHotPlug[7]" = "1" - register "PcieClkSrcUsage[3]" = "7" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpAdvancedErrorReporting[7]" = "1" - - # Enable NVMe PCIE 9 using clk 1 - register "PchPcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[1]" = "8" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieRpAdvancedErrorReporting[8]" = "1" - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoPci, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, }"
register "SerialIoGSpiMode" = "{ @@ -121,10 +92,38 @@ end device ref heci1 on end device ref sata on end - device ref pcie_rp5 on end #PCIE5 WLAN - device ref pcie_rp6 on end #PCIE6 WWAN - device ref pcie_rp8 on end #PCIE8 SD card - device ref pcie_rp9 on end #PCIE9-12 SSD + device ref pcie_rp5 on + # Enable WLAN PCIE 5 using clk 2 + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE5 WLAN + device ref pcie_rp6 on + # Enable WWAN PCIE 6 using clk 5 + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE6 WWAN + device ref pcie_rp8 on + # Enable SD Card PCIE 8 using clk 3 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE8 SD card + device ref pcie_rp9 on + # Enable NVMe PCIE 9 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE9-12 SSD device ref uart0 on end device ref gspi1 on end device ref pch_espi on diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 0dd1456..eb7be69 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -40,49 +40,58 @@ register "PrmrrSize" = "0"
# Enable PCH PCIE RP 5 using CLK 2 - register "PchPcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcUsage[2]" = "0x4" - register "PcieRpClkReqDetect[4]" = "1" + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }"
# Enable PCH PCIE RP 6 using CLK 5 - register "PchPcieRpEnable[5]" = "1" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcUsage[5]" = "0x5" - register "PcieRpClkReqDetect[5]" = "1" + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT, + }"
- # Enable PCH PCIE RP 8 using CLK 6 - register "PchPcieRpEnable[7]" = "1" - register "PcieClkSrcUsage[6]" = "PCIE_CLK_FREE" # CLK 6 is using free running CLK + # Enable PCH PCIE RP 8 using free running CLK (0x80) + # Clock source is shared with LAN and hence marked as free running. + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING"
# Enable PCH PCIE RP 9 using CLK 1 - register "PchPcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcUsage[1]" = "0x8" - register "PcieRpClkReqDetect[8]" = "1" + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }"
# Enable PCH PCIE RP 11 for optane - register "PchPcieRpEnable[10]" = "1" + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + # Hybrid storage mode register "HybridStorageMode" = "1"
# Enable CPU PCIE RP 1 using CLK 0 - register "CpuPcieRpEnable[0]" = "1" - register "PcieClkSrcUsage[0]" = "0x40" + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + }"
# Enable CPU PCIE RP 2 using CLK 3 - register "CpuPcieRpEnable[1]" = "1" - register "PcieClkSrcUsage[3]" = "0x41" + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .clk_req = 3, + .clk_src = 3, + }"
# Enable CPU PCIE RP 3 using CLK 4 - register "CpuPcieRpEnable[2]" = "1" - register "PcieClkSrcUsage[4]" = "0x42" - - # W/A to FSP issue where FSP is using PCH PCIE port - # enable UPD to download FW on CPU PCIE - register "PchPcieRpEnable[0]" = "1" - register "PchPcieRpEnable[2]" = "1" - register "PchPcieRpEnable[3]" = "1" + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_req = 4, + .clk_src = 4, + }"
register "SataSalpSupport" = "1"
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 0f932ce..13e77cf 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -19,10 +19,6 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6
-#define PCIE_CLK_NOTUSED 0xFF -#define PCIE_CLK_LAN 0x70 -#define PCIE_CLK_FREE 0x80 - struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */ @@ -122,31 +118,9 @@ uint8_t PchHdaIDispLinkFrequency; uint8_t PchHdaIDispCodecDisconnect;
- /* CPU PCIe Root Ports */ - uint8_t CpuPcieRpEnable[CONFIG_MAX_CPU_ROOT_PORTS]; - - /* PCH PCIe Root Ports */ - uint8_t PchPcieRpEnable[CONFIG_MAX_PCH_ROOT_PORTS]; - uint8_t PcieRpHotPlug[CONFIG_MAX_PCH_ROOT_PORTS]; - /* PCIe output clocks type to PCIe devices. - * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, - * 0xFF: not used */ - uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; - /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to - * clksrc. */ - uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ]; - - /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; - - /* PCIe RP L1 substate */ - enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; - - /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; - - /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ - uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_PCH_ROOT_PORTS]; + struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS]; + struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS]; + uint8_t pcie_clk_config_flag[CONFIG_MAX_PCIE_CLOCK_SRC];
/* Gfx related */ enum { diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 35f7a3c..6e6f1af 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -15,6 +15,7 @@ #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> #include <string.h> @@ -93,6 +94,7 @@ const struct microcode *microcode_file; size_t microcode_len; FSP_S_CONFIG *params = &supd->FspsConfig; + uint32_t enable_mask;
struct device *dev; struct soc_intel_alderlake_config *config; @@ -270,19 +272,19 @@ /* Enable Hybrid storage auto detection */ params->HybridStorageMode = config->HybridStorageMode;
+ enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { + if (!(enable_mask & BIT(i))) + continue; + const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; params->PcieRpL1Substates[i] = - get_l1_substate_control(config->PcieRpL1Substates[i]); - params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; - params->PcieRpAdvancedErrorReporting[i] = - config->PcieRpAdvancedErrorReporting[i]; - params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; + get_l1_substate_control(rp_cfg->PcieRpL1Substates); + params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); + params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); + params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); + params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); }
- /* Enable ClkReqDetect for enabled port */ - memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, - sizeof(config->PcieRpClkReqDetect)); - params->PmSupport = 1; params->Hwp = 1; params->Cx = 1; diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 0154cb4..3852467 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -7,20 +7,58 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/mp_init.h> +#include <intelblocks/pcie_rp.h> #include <soc/gpio_soc_defs.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/romstage.h> #include <soc/soc_chip.h> #include <string.h>
+#define FSP_CLK_NOTUSED 0xFF +#define FSP_CLK_LAN 0x70 +#define FSP_CLK_FREE_RUNNING 0x80 + +#define CPU_PCIE_BASE 0x40 + +enum pcie_rp_type { + PCH_PCIE_RP, + CPU_PCIE_RP, +}; + +static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number) +{ + assert(type == PCH_PCIE_RP || type == CPU_PCIE_RP); + + if (type == PCH_PCIE_RP) + return rp_number; + else // type == CPU_PCIE_RP + return CPU_PCIE_BASE + rp_number; +} + +static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_type type, + const struct pcie_rp_config *cfg, size_t cfg_count) +{ + size_t i; + + for (i = 0; i < cfg_count; i++) { + if (!(en_mask & BIT(i))) + continue; + if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED) + continue; + if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) + m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); + } +} + static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { - unsigned int i; - uint32_t mask = 0; const struct device *dev; + unsigned int i;
dev = pcidev_path_on_root(SA_DEVFN_IGD); if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev)) @@ -42,18 +80,6 @@ /* Set CpuRatio to match existing MSR value */ m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff;
- for (i = 0; i < ARRAY_SIZE(config->PchPcieRpEnable); i++) { - if (config->PchPcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; - - memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, - sizeof(config->PcieClkSrcUsage)); - - memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, - sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ @@ -116,6 +142,27 @@ m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency; m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;
+ /* Disable all PCIe clock sources by default. And set RP irrelevant clock. */ + for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) { + if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING; + else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN) + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN; + else + m_cfg->PcieClkSrcUsage[i] = FSP_CLK_NOTUSED; + m_cfg->PcieClkSrcClkReq[i] = FSP_CLK_NOTUSED; + } + + /* PCIE ports */ + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); + pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, PCH_PCIE_RP, config->pch_pcie_rp, + CONFIG_MAX_PCH_ROOT_PORTS); + + /* CPU PCIE ports */ + m_cfg->CpuPcieRpEnableMask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); + pcie_rp_init(m_cfg, m_cfg->CpuPcieRpEnableMask, CPU_PCIE_RP, config->cpu_pcie_rp, + CONFIG_MAX_CPU_ROOT_PORTS); + /* ISH */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); m_cfg->PchIshEnable = is_dev_enabled(dev); @@ -156,13 +203,6 @@ /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
- mask = 0; - for (i = 0; i < ARRAY_SIZE(config->CpuPcieRpEnable); i++) { - if (config->CpuPcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->CpuPcieRpEnableMask = mask; - m_cfg->TmeEnable = CONFIG(INTEL_TME);
/* Skip GPIO configuration from FSP */
Attention is currently required from: EricR Lai. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 72:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/0fb8c8fc_ac0f667d PS69, Line 123: uint8_t Was this meant to be `enum pcie_clk_src_flags`?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
Patch Set 72:
(1 comment)
File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/bcd462ab_35ad0d4d PS69, Line 123: uint8_t
Was this meant to be `enum pcie_clk_src_flags`?
yes this is used for enum pcie_clk_src_flags.
-
Angel Pons (Code Review) -
build bot (Jenkins) (Code Review)
-
EricR Lai (Code Review)
-
Furquan Shaikh (Code Review)
-
Meera Ravindranath (Code Review)
-
Michael Niewöhner (Code Review)
-
Nico Huber (Code Review)
-
Patrick Georgi (Code Review)
-
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)