[coreboot-gerrit] Change in coreboot[master]: mb/intel/adlrvp: Add ADL-P ramstage mainboard code

[Subrata Banik (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Martin Roth, Tim Wawrzynczak, Angel Pons,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46265

to look at the new patch set (#9).

Change subject: mb/intel/adlrvp: Add ADL-P ramstage mainboard code
......................................................................

mb/intel/adlrvp: Add ADL-P ramstage mainboard code

List of changes:
1. Add devicetree.cb config parameters related to FSP-S UPD
2. Configure GPIO as per ADL-P RVP
3. Add files required for ramstage(ec.c, mainboard.c)
4. Add smihandler.c for SMM
5. Add devicetree changes as below
- USB OC PIN programing
- GPE configuration
- SATA port mapping
- LPSS configuration
- Audio configuration
- IA common SoC configuration
- EDP configuration
- TCSS USB configuration
- Enable S0ix

TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with
UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till
depthcharge payload.

Change-Id: I120885956c88babfa09d24ce1079d49306919b8a
Signed-off-by: Subrata Banik 
---
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/ec.c
A src/mainboard/intel/adlrvp/mainboard.c
A src/mainboard/intel/adlrvp/smihandler.c
M src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc
M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
A src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c
A src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h
M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h
9 files changed, 594 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/46265/9