Hello V Sowmya, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Maulik V Vaghela, Angel Pons, Aamir Bohra, Aaron Durbin, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44014
to look at the new patch set (#7).
Change subject: src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource ......................................................................
src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource
Ideally don't need to mark the entire top_of_ram till TOLUD range (used for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as cacheable for OS usage as coreboot already done with mpinit w/ smm relocation early.
TEST=Able to build and boot ICL, TGL RVP.
Without this CL :
PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a
With this CL :
PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index 9
No changes observed with MTRRs snapshot.
Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 2 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44014/7