Weiyi Lu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37136 )
Change subject: soc/mediatek/mt8183: disable BBLPM of DCXO core ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37136/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37136/2//COMMIT_MSG@7 PS2, Line 7: mediatek/mt8183
soc/mediatek/mt8183
Done
https://review.coreboot.org/c/coreboot/+/37136/2//COMMIT_MSG@9 PS2, Line 9: When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter : will have DCXO core to enter Baseband Low-Power Mode(BBLPM). : Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided : and crystal voltage will drop from 1.8V to 0.7V or lower. : In order to ensure the stability by always outputting an accuarate system clock : when system is running. We should disable BBLPM when only XO_SOC enabled.
Limit line length to 72 characters.
Done
https://review.coreboot.org/c/coreboot/+/37136/2//COMMIT_MSG@15 PS2, Line 15:
Is there a bug for this issue?
no, it's a volunteer patch