View Change
3 comments:
Commit Message:
Patch Set #2, Line 7: mediatek/mt8183
soc/mediatek/mt8183
Done
Patch Set #2, Line 9:
When we only enable XO_SOC and mask most BBLPM requests, the BBLPM HW arbiter
will have DCXO core to enter Baseband Low-Power Mode(BBLPM).
Under BBLPM mode, inaccurate(about 1.5KHz offset) 26MHz clocks from crystal is provided
and crystal voltage will drop from 1.8V to 0.7V or lower.
In order to ensure the stability by always outputting an accuarate system clock
when system is running. We should disable BBLPM when only XO_SOC enabled.
Limit line length to 72 characters.
Done
Patch Set #2, Line 15:
Is there a bug for this issue?
no, it's a volunteer patch
To view, visit change 37136. To unsubscribe, or for help writing mail filters, visit settings.
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iea72a964507a19735cf92e3774cd8a94c06545b2
Gerrit-Change-Number: 37136
Gerrit-PatchSet: 3
Gerrit-Owner: Weiyi Lu <weiyi.lu@mediatek.corp-partner.google.com>
Gerrit-Reviewer: Hung-Te Lin <hungte@chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner@chromium.org>
Gerrit-Reviewer: Weiyi Lu <weiyi.lu@mediatek.com>
Gerrit-Reviewer: Weiyi Lu <weiyi.lu@mediatek.corp-partner.google.com>
Gerrit-Reviewer: You-Cheng Syu <youcheng@google.com>
Gerrit-Reviewer: Yu-Ping Wu <yupingso@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: SJ Huang <sj.huang@mediatek.corp-partner.google.com>
Gerrit-Comment-Date: Tue, 26 Nov 2019 05:25:42 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Yu-Ping Wu <yupingso@google.com>
Gerrit-MessageType: comment