[coreboot-gerrit] Change in coreboot[master]: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA

[Michał Żygowski (Code Review)]

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39970 )

Change subject: mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA
......................................................................

mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA

Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe
ClockPM is enabled in AGESA PCIe initialization structures. Disable it
to allow platform to boot with such devices. coreboot driver enables
the ClockPM correctly on such devices anyway.

Signed-off-by: Michał Żygowski 
Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/mainboard/pcengines/apu2/OemCustomize.c
1 file changed, 5 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c
index e47a2c8..8b6cd03 100644
--- a/src/mainboard/pcengines/apu2/OemCustomize.c
+++ b/src/mainboard/pcengines/apu2/OemCustomize.c
@@ -35,7 +35,7 @@
    			PcieGenMaxSupported,
    			AspmL0sL1,
    			PCIE_PORT3_RESET_ID,
-				ClkPmSupportEnabled)
+				0)
    },
    /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
    {
@@ -47,7 +47,7 @@
    			PcieGenMaxSupported,
    			AspmL0sL1,
    			PCIE_NIC_RESET_ID,
-				ClkPmSupportEnabled)
+				0)
    },
    /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
    {
@@ -59,7 +59,7 @@
    			PcieGenMaxSupported,
    			AspmL0sL1,
    			PCIE_NIC_RESET_ID,
-				ClkPmSupportEnabled)
+				0)
    },
    /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
    {
@@ -71,7 +71,7 @@
    			PcieGenMaxSupported,
    			AspmL0sL1,
    			PCIE_NIC_RESET_ID,
-				ClkPmSupportEnabled)
+				0)
    },
    /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
    {
@@ -83,7 +83,7 @@
    			PcieGenMaxSupported,
    			AspmL0sL1,
    			PCIE_GFX_RESET_ID,
-				ClkPmSupportEnabled)
+				0)
    }
 };