Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37331 )
Change subject: amd/agesa/family14: implement C bootblock ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig File src/cpu/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/cpu/amd/agesa/Kconfig@6... PS1, Line 60: config S3_DATA_POS Separate commit for this please. You probably have this done before I am ready to remove this entirely. Or reduce bootblock size to 32KiB. I think we use <2KiB of S3_DATA_SIZE to be honest but that's the more thorough fix for a later date.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/K... File src/northbridge/amd/agesa/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/K... PS1, Line 20: select ROMCC_BOOTBLOCK Already done with future rebase.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 21: romstage-y += nb_util.c We probably won't have this file added.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 26: void amd_initmmio(void) We probably want this named better. Neither PCI MMONF or that MTRR setup seems platform-specific.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 41: pci_write_config32(dev, 0xE4, (AMD_APU_SSID << 0x10) | AMD_APU_SVID); This might be just bogus. At least there should be no reason to call this so early and for each core separately.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family14/nb_util.c:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 19: void *get_ap_entry_ptr(void) I think we will have these two functions implemented in soc/amd/common. I see no reason why these should be per-platform.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family15tn/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 17: select ROMCC_BOOTBLOCK I have pushed patch to flag each board individually to ROMCC_BOOTBLOCK for the transition period.
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... File src/northbridge/amd/agesa/family16kb/Kconfig:
https://review.coreboot.org/c/coreboot/+/37331/1/src/northbridge/amd/agesa/f... PS1, Line 18: select ROMCC_BOOTBLOCK as before