[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Do memory pll init before calibration

[Xi Chen (Code Review)]

Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )

Change subject: soc/mediatek/mt8192: Do memory pll init before calibration
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Patch Set 50:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44702/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44702/6//COMMIT_MSG@8 
PS6, Line 8:
> Please elaborate. […]

PLL initialization is dramc and ddrphy reference clock, it did the basic clock settings for dramc/ddrphy working well.