[coreboot-gerrit] Change in coreboot[master]: mb/asrock/h110m/romstage.c: Correct FSP-M UPDs

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46246 )

Change subject: mb/asrock/h110m/romstage.c: Correct FSP-M UPDs
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46246/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/46246/1//COMMIT_MSG@9 
PS1, Line 9: not apply to DDR4 configurations
> does only apply to LPDDR* configurations

I've no idea if DDR5 could use the byte maps. Plus, the board at hand only supports DDR4, so why would I talk about LPDDR and risk being wrong about it? You know, I don't like being mistaken in writings that will eventually get set in stone (e.g. commit messages)... 😆