[coreboot-gerrit] Change in coreboot[master]: mb/ocp/tiogapass/devicetree.cb: Add P2SB device

[Marc Jones (Code Review)]

Marc Jones has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48654 )

Change subject: mb/ocp/tiogapass/devicetree.cb: Add P2SB device
......................................................................

mb/ocp/tiogapass/devicetree.cb: Add P2SB device

This fixes ocp/tiagopass not booting as after FSP-S the P2SB is
accessed to read out or reconfigure the HPET and PCH IOAPIC BDF.

Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654
Reviewed-by: Marc Jones 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/ocp/tiogapass/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marc Jones: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb
index 008633b..488f677 100644
--- a/src/mainboard/ocp/tiogapass/devicetree.cb
+++ b/src/mainboard/ocp/tiogapass/devicetree.cb
@@ -77,6 +77,7 @@
    			register "bmc_boot_timeout" = "90"
    		end
    	end # Intel Corporation C621 Series Chipset LPC/eSPI Controller
+		device pci 1f.1 hidden end # p2sb
    	device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller
    	device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus
    	device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller