[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/skylake: Set FSP options for PEG port

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/32045

to look at the new patch set (#10).

Change subject: soc/intel/skylake: Set FSP options for PEG port
......................................................................

soc/intel/skylake: Set FSP options for PEG port

FSP options list (for each PEG port):
  - PegXEnable,
  - PegXMaxLinkWidth,
  - PegXMaxLinkSpeed,
  - PegXPowerDownUnusedLanes,
  - PegXGen3EqPh2Enable,
  - PegXGen3EqPh3Method.

Add PegMaxLinkWidth to chip.h. This option overrides the number of
active lines from the devicetree.cb for each enabled PEG port (for
example for boards that use x4 instead of x16 lines in PEG0). If the
PegMaxLinkWidth is not defined, the port uses the maximum possible
number of lines.

To enable or disable the corresponding PEG root port you need to add
to the devicetree.cb:

device pci 01.0 on  end # enable PEG0 root port
  device pci 01.1 off end # do not configure PEG1

If PEG port is not defined in the devicetree, it will be disabled in
FSP.

It has been tested on ASRock H110M-DVS motherboard (Skylake i5-6600
CPU).

Change-Id: I23708f7060edf08739adf61fe61a419329907563
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/include/soc/pci_devs.h
M src/soc/intel/skylake/romstage/romstage_fsp20.c
3 files changed, 87 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32045/10