Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45827 )
Change subject: soc/intel/braswell: Increase dcache size ......................................................................
soc/intel/braswell: Increase dcache size
Need to increase the DRAM cache size for braswell as the was getting the compilation error "Cache as RAM area is too full" when moving the mrc_cache writeback to romstage. We need to increase this first before landing the CL moving mrc_cache writeback to romstage.
BUG=b:150502246 BRANCH=None TEST=Able to successfully compile braswell boards
Change-Id: I1538d504ddad8654c79a789e58ffe6b11b5d544c Signed-off-by: Shelley Chen shchen@google.com --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/45827/1
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 5c9988c..077b5a1 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -96,7 +96,7 @@
config DCACHE_RAM_SIZE hex - default 0x4000 + default 0x5000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE