Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32126 )
Change subject: mb/google/hatch: Unlock GPIO pads ......................................................................
mb/google/hatch: Unlock GPIO pads
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST.
BUG=b:128686027 BRANCH=None TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register. localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080 0x00000000 localhost /sys/class/gpio # echo 212 > export
Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Signed-off-by: Krishna Prasad Bhat krishna.p.bhat.d@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index dc7cc24..984852f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -73,6 +73,8 @@ register "DdiPortBHpd" = "1" register "DdiPortCHpd" = "1" register "tcc_offset" = "10" # TCC of 90C + # Unlock GPIO pads + register "PchUnlockGpioPads" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1