[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Rework PCH ID cache

[Angel Pons (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/49168

to look at the new patch set (#2).

Change subject: sb/intel/bd82x6x: Rework PCH ID cache
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sb/intel/bd82x6x: Rework PCH ID cache

Work around a romstage restriction. Globals (or static variables) cannot
be initialized to a non-zero value because there's no data section. Note
that the revision ID for stepping A0 is zero, so `pch_silicon_revision`
will no longer use the cached value for this PCH stepping. Since it is a
pre-production stepping, it is most likely not used anywhere anymore.

Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd
Signed-off-by: Angel Pons 
---
M src/southbridge/intel/bd82x6x/common.c
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/49168/2