[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block/cpu/car: Enable caching before FSP-T

[Gaggery Tsai (Code Review)]

Hello Patrick Rudolph, Pratikkumar V Prajapati, Subrata Banik, Balaji Manigandan, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38252

to look at the new patch set (#5).

Change subject: soc/intel/common/block/cpu/car: Enable caching before FSP-T
......................................................................

soc/intel/common/block/cpu/car: Enable caching before FSP-T

This patch is required for Boot Guard enabled platform. When system
is powered on, cache is default enabled. BIOS is fobidden to disable
cache while in NEM mode with BtG enabled.

TEST=Stitch boot guard ACM with signed KM and BPM &&
     Enable FSP-T and boot all the way to the OS &&
     Read MSR 0x13a and esnure boot guard verified boot and
     measured boot are enabled.

Change-Id: Ie1def754f7b0024725638fcea481fd3273ef3d24
Signed-off-by: Gaggery Tsai 
---
M src/cpu/x86/16bit/entry16.inc
M src/cpu/x86/Kconfig
2 files changed, 34 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38252/5