Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45828 )
Change subject: mb/intel/tglrvp: Enable Pcie WWAN m.2 ......................................................................
mb/intel/tglrvp: Enable Pcie WWAN m.2
Enables Pcie M.2 support for WWAN and disable M.2 USB. RP4 is already on and PcieRpEnable[3] is enabled. Clock source 2 is already configured. Added missing gpio configuration.
BUG=none TEST=Boot to OS, check WWAN functionality
Change-Id: Ie9b7915062b2ef65d881d478e64322c0b8765614 Signed-off-by: Bora Guvendik bora.guvendik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45828 Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 20 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 2abdce4..09ab258 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index c9de9c6..51b301d 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -104,6 +104,15 @@ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ };
const struct pad_config *variant_gpio_table(size_t *num) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b46a1cf..25c2293 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -20,7 +20,7 @@ register "SmbusEnable" = "1"
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 303350b..77da5cc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -100,6 +100,15 @@ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), /* B22 : GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + + /* WWAN */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* WWAN_PWREN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* CLK SRC 2 */ + PAD_CFG_GPI_SCI(GPP_C9, NONE, DEEP, LEVEL, INVERT), /* WWAN_WAKE_N */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* FULL_CARD_POWER_OFF_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_RST_N */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PERST_N */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_DISABLE_N */ };
const struct pad_config *variant_gpio_table(size_t *num)