Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/44700
to review the following change.
Change subject: soc/mediatek/mt8192: Do dramc init settings ......................................................................
soc/mediatek/mt8192: Do dramc init settings
Signed-off-by: Huayang Duan huayang.duan@mediatek.com Change-Id: Ie4877b69de1bfa4ff981d8eb386efbddb9e0f5c2 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/dramc_pi_basic_api.c A src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/emi.c 5 files changed, 242 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44700/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index dd80beb..e82f182 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -16,6 +16,7 @@ verstage-y += ../common/uart.c
romstage-y += ../common/cbmem.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_utility.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c new file mode 100644 index 0000000..9b1216c --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <string.h> +#include <timer.h> + +void global_option_init(struct ddr_cali *cali) +{ +} + +void dfs_init_for_calibration(const struct ddr_cali *cali) +{ +} diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c new file mode 100644 index 0000000..e2c7500 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/mt6359p.h> + +static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("Set DRAM vcore voltage to %u\n", vcore); + mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); +} + +static void dramc_calibration_all_channels(struct ddr_cali *cali) +{ +} + +void init_dram(const struct dramc_data *dparam) +{ + u32 bc_bak; + u8 k_shuffle, k_shuffle_end; + u8 pll_mode = 0; + bool first_freq_k = true; + + struct ddr_cali cali = {0}; + struct mr_values mr_value; + const struct ddr_base_info *ddr_info = &dparam->ddr_info; + + cali.pll_mode = &pll_mode; + cali.mr_value = &mr_value; + cali.support_ranks = ddr_info->support_ranks; + cali.cbt_mode[RANK_0] = ddr_info->cbt_mode[RANK_0]; + cali.cbt_mode[RANK_1] = ddr_info->cbt_mode[RANK_1]; + cali.emi_config = &ddr_info->emi_config; + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + global_option_init(&cali); + bc_bak = dramc_get_broadcast(); + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + dramc_set_broadcast(bc_bak); + + if (ddr_info->config_dvfs == DRAMC_ENABLE_DVFS) + k_shuffle_end = CALI_SEQ_MAX; + else + k_shuffle_end = CALI_SEQ1; + + for (k_shuffle = CALI_SEQ0; k_shuffle < k_shuffle_end; k_shuffle++) { + set_cali_datas(&cali, dparam, k_shuffle); + set_vcore_voltage_for_each_freq(&cali); + dfs_init_for_calibration(&cali); + + dramc_calibration_all_channels(&cali); + + first_freq_k= false; + } +} diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c new file mode 100644 index 0000000..526059a --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -0,0 +1,166 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> +#include <soc/infracfg.h> + +struct dfs_frequency_table { + u32 frequency; + dram_freq_grp freq_group; + dram_div_mode div_mode; + dram_dfs_shu shuffle_saved; + vref_cali_mode vref_cali; + u32 vcore; +}; + +static const struct dfs_frequency_table freq_shuffle_table[DRAM_DFS_SHU_MAX] = { + /* frequency freq_group div_mode shuffle_saved vref_cali vcore*/ + [CALI_SEQ0] = {800, DDRFREQ_800, DIV8_MODE, DRAM_DFS_SHU4, VREF_CALI_ON, 650000}, + [CALI_SEQ1] = {1200, DDRFREQ_1200, DIV8_MODE, DRAM_DFS_SHU2, VREF_CALI_ON, 662500}, + [CALI_SEQ2] = {600, DDRFREQ_600, DIV8_MODE, DRAM_DFS_SHU5, VREF_CALI_OFF, 650000}, + [CALI_SEQ3] = {933, DDRFREQ_933, DIV8_MODE, DRAM_DFS_SHU3, VREF_CALI_OFF, 662500}, + [CALI_SEQ4] = {400, DDRFREQ_400, DIV4_MODE, DRAM_DFS_SHU6, VREF_CALI_OFF, 650000}, + [CALI_SEQ5] = {2133, DDRFREQ_2133, DIV8_MODE, DRAM_DFS_SHU0, VREF_CALI_ON, 725000}, + [CALI_SEQ6] = {1600, DDRFREQ_1600, DIV8_MODE, DRAM_DFS_SHU1, VREF_CALI_OFF, 687500}, +}; + +void dramc_set_broadcast(u32 onoff) +{ + write32(&mt8192_infracfg->dramc_wbr, onoff); +} + +u32 dramc_get_broadcast(void) +{ + return read32(&mt8192_infracfg->dramc_wbr); +} + +u8 get_fsp(const struct ddr_cali *cali) +{ + return cali->fsp; +} + +dram_div_mode get_div_mode(const struct ddr_cali *cali) +{ + return cali->div_mode; +} + +dram_freq_grp get_freq_group(const struct ddr_cali *cali) +{ + return cali->freq_group; +} + +dbi_mode get_write_dbi(const struct ddr_cali *cali) +{ + return cali->w_dbi[get_fsp(cali)]; +} + +dram_odt_state get_odt_state(const struct ddr_cali *cali) +{ + return cali->odt_onoff; +} + +dram_dfs_shu get_shu(const struct ddr_cali *cali) +{ + return cali->shu; +} + +dram_cbt_mode get_cbt_mode(const struct ddr_cali *cali) +{ + return cali->cbt_mode[cali->rank]; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ + return cali->vcore_voltage; +} + +u32 get_frequency(const struct ddr_cali *cali) +{ + return cali->frequency; +} + +vref_cali_mode get_vref_cali(const struct ddr_cali *cali) +{ + return cali->vref_cali; +} + +dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali) +{ + return cali->pinmux_type; +} + +u8 get_mck2ui_div_shift(const struct ddr_cali *cali) +{ + if (get_div_mode(cali) == DIV4_MODE) + return 2; + else + return 3; +} + +dram_dfs_shu get_shu_save_by_k_shu(dram_cali_seq k_shu) +{ + return freq_shuffle_table[k_shu].shuffle_saved; +} + +dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].freq_group; + + dramc_err("Invalid shuffle:%d\n", shu); + return DDRFREQ_800; +} + +u32 get_frequency_by_shu(dram_dfs_shu shu) +{ + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].shuffle_saved == shu) + return freq_shuffle_table[k_shu].frequency; + + dramc_err("Invalid shuffle:%d\n", shu); + return 800; +} + +dram_freq_grp get_highest_freq_group(void) +{ + dram_freq_grp highest_freq = DDRFREQ_800; + + for (u8 k_shu = CALI_SEQ0; k_shu < CALI_SEQ_MAX; k_shu++) + if (freq_shuffle_table[k_shu].freq_group > highest_freq) + highest_freq = freq_shuffle_table[k_shu].freq_group; + + dramc_dbg("Highest freq is :%d\n", highest_freq); + return highest_freq; +} + +void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_shu) +{ + cali->chn = CHANNEL_A; + cali->rank = RANK_0; + cali->fsp = (freq_shuffle_table[k_shu].freq_group < DDRFREQ_1600) ? FSP_0 : FSP_1; + cali->w_dbi[FSP_0] = DBI_OFF; + cali->w_dbi[FSP_1] = DBI_ON; + cali->frequency = freq_shuffle_table[k_shu].frequency; + cali->freq_group = freq_shuffle_table[k_shu].freq_group; + cali->div_mode = freq_shuffle_table[k_shu].div_mode; + cali->shu = freq_shuffle_table[k_shu].shuffle_saved; + cali->vref_cali = freq_shuffle_table[k_shu].vref_cali; + cali->vcore_voltage = freq_shuffle_table[k_shu].vcore; + cali->odt_onoff = (cali->fsp == FSP_0) ? ODT_OFF : ODT_ON; + cali->params = &dparam->freq_params[cali->shu]; + + dramc_dbg("cali data(size:%ld) use fsp:%d, freq_group:%d, div_mode:%d, shu:%d, vref_cali:%d, odt_onoff:%d, vcore:%d\n", + sizeof(*cali), cali->fsp, cali->freq_group, cali->div_mode, cali->shu, + cali->vref_cali, cali->odt_onoff, cali->vcore_voltage); +} + +void dramc_auto_refresh_switch(u8 chn, bool enable) +{ + SET32_BITFIELDS(&ch[chn].ao.refctrl0, REFCTRL0_REFDIS, enable ? 0 : 1); + + if (!enable) { + udelay(READ32_BITFIELD(&ch[chn].nao.misc_statusa, + MISC_STATUSA_REFRESH_QUEUE_CNT)); + } +} diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c index 9e48918..f83acd3 100644 --- a/src/soc/mediatek/mt8192/emi.c +++ b/src/soc/mediatek/mt8192/emi.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#include <soc/emi.h> +#include <soc/dramc_pi_api.h>
size_t sdram_size(void) { @@ -11,4 +11,5 @@
void mt_set_emi(const struct dramc_data *dparam) { + init_dram(dparam); }