[coreboot-gerrit] Change in ...coreboot[master]: Documentation: Explain DDR3 read training

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32334

Change subject: Documentation: Explain DDR3 read training
......................................................................

Documentation: Explain DDR3 read training

Add lots of colorful graphics to explain DDR3 read training in
detail, what is done inside MCH and what needs to be done on
firmware level.

Besides read training give a short explenation what DDR3 "FlyBy" is
and compare it with DDR2 DIMMs.

Besides the SVG all sources files are added.

Change-Id: Ib477bd332984c397289404cfc33c65a2d4469257
Signed-off-by: Patrick Rudolph 
---
M Documentation/getting_started/index.md
A Documentation/getting_started/ram_initialization/16delay.dia
A Documentation/getting_started/ram_initialization/16delay.svg
A Documentation/getting_started/ram_initialization/64delay.dia
A Documentation/getting_started/ram_initialization/64delay.svg
A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.dia
A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.svg
A Documentation/getting_started/ram_initialization/ddr3_flyby.md
A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia
A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg
A Documentation/getting_started/ram_initialization/index.md
A Documentation/getting_started/ram_initialization/read_training.dia
A Documentation/getting_started/ram_initialization/read_training.svg
A Documentation/getting_started/ram_initialization/read_training2.dia
A Documentation/getting_started/ram_initialization/read_training2.svg
A Documentation/getting_started/ram_initialization/read_training3.dia
A Documentation/getting_started/ram_initialization/read_training3.svg
A Documentation/getting_started/ram_initialization/read_training_pattern.dia
A Documentation/getting_started/ram_initialization/read_training_pattern.svg
A Documentation/getting_started/ram_initialization/readtraining.md
A Documentation/getting_started/ram_initialization/recv_blocks.dia
A Documentation/getting_started/ram_initialization/recv_blocks.svg
22 files changed, 1,989 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32334/1

diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md
index 52d873e..a265c5d 100644
--- a/Documentation/getting_started/index.md
+++ b/Documentation/getting_started/index.md
@@ -7,3 +7,4 @@
 * [Gerrit Guidelines](gerrit_guidelines.md)
 * [Documentation License](license.md)
 * [Writing Documentation](writing_documentation.md)
+* [DDR3 memory initialization](ram_initialization/index.md)
diff --git a/Documentation/getting_started/ram_initialization/16delay.dia b/Documentation/getting_started/ram_initialization/16delay.dia
new file mode 100644
index 0000000..d0e0095
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Binary files differ
diff --git a/Documentation/getting_started/ram_initialization/16delay.svg b/Documentation/getting_started/ram_initialization/16delay.svg
new file mode 100644
index 0000000..f661ddd
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diff --git a/Documentation/getting_started/ram_initialization/ddr3_flyby.md b/Documentation/getting_started/ram_initialization/ddr3_flyby.md
new file mode 100644
index 0000000..fc6f7a7
--- /dev/null
+++ b/Documentation/getting_started/ram_initialization/ddr3_flyby.md
@@ -0,0 +1,36 @@
+# DDR3 Flyby technology
+
+# DDR3 vs DDR2
+To ease the DIMM routing at high frequencies, the "fly-by" topology has been
+introduced starting with DDR3.
+It's called "fly-by" as CLK and CMD is routed below the ICs in a daisy chain and
+it includes very short stubs to each memory device in the chain to reduce the
+reflections. As every DIMM only needs to terminate the line once at end of PCB,
+the DC resistance is much lower as on DDR2 "tree" routing topology, which did
+terminate on every IC.
+
+The disadvantage of "fly-by" is the more complex memory training that needs to
+be done to find the DATA lane skew.
+
+After the skew has been measured, the DATA lanes needs to be delayed by the 
+memory controller, to make sure all signals are still synchronous to the CLK,
+as seen be the memory controller (on READ) or the DRAM (on WRITE).
+
+![][flyby]
+
+[flyby]: ddr3_vs_ddr2.svg
+
+```eval_rst
++---------------------------+------------+----------------+
+| Feature                   | DDR2       |           DDR3 |
++===========================+============+================+
+| Frequency                 | 200-533    |        400-800 |
++---------------------------+------------+----------------+
+| Routing                   | complex    |           easy |
++---------------------------+------------+----------------+
+| Termination DC resistance | very high  |            low |
++---------------------------+------------+----------------+
+| Memory training           | easy       |        complex |
++---------------------------+------------+----------------+
+```
+
diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia
new file mode 100644
index 0000000..e4b4d09
--- /dev/null
+++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia
Binary files differ
diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg
new file mode 100644
index 0000000..0b8db34
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diff --git a/Documentation/getting_started/ram_initialization/index.md b/Documentation/getting_started/ram_initialization/index.md
new file mode 100644
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+++ b/Documentation/getting_started/ram_initialization/index.md
@@ -0,0 +1,4 @@
+# DDR3 RAM initialization
+
+* [DDR3 Flyby](ddr3_flyby.md)
+* [Read training](readtraining.md)
diff --git a/Documentation/getting_started/ram_initialization/read_training.dia b/Documentation/getting_started/ram_initialization/read_training.dia
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index 0000000..ca6d57d
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+    <tspan x="550.86" y="373.532">READ</tspan>
+  </text>
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+  <line style="fill: none; fill-opacity:0; stroke-width: 4; stroke: #0000ff" x1="1367.24" y1="246.292" x2="1464.77" y2="246.48"/>
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+  <text font-size="17.3172" style="fill: #0000ff;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="233.512" y="271.172">
+    <tspan x="233.512" y="271.172">CLK</tspan>
+  </text>
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+    <tspan x="234.006" y="371.06">CMD</tspan>
+  </text>
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+    <tspan x="232.196" y="466.231">DQS</tspan>
+  </text>
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+    <tspan x="1525.05" y="516.559">time</tspan>
+  </text>
+  <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="232.768" y="207.386">
+    <tspan x="232.768" y="207.386">voltage</tspan>
+  </text>
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+    <tspan x="630.938" y="546.092">tCAS_latency</tspan>
+  </text>
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+    <tspan x="755.906" y="172.258">DDR3 Read Command as seen by DRAM</tspan>
+  </text>
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diff --git a/Documentation/getting_started/ram_initialization/readtraining.md b/Documentation/getting_started/ram_initialization/readtraining.md
new file mode 100644
index 0000000..e69418a
--- /dev/null
+++ b/Documentation/getting_started/ram_initialization/readtraining.md
@@ -0,0 +1,116 @@
+# Welcome to the coreboot documentation
+
+## DDR3 Fly-by
+
+DDR3 uses the [FlyBy routing] for clock, address and command signals.
+Due to that routing the DATA/DQS signals are not synchronous the CLK as seen
+by the MCH.
+
+![][skew]
+
+[skew]: DRAM_data_clock_lanes_skew.svg
+
+On a READ instruction the DATA seen by MCH is delayed by:
+
+```
+t_LANEx_delay = t_CLK + t_CASLatency + t_LANEx + t_CLKSKEWx
+```
+
+where `t_CLK` and `t_LANEx` depend on the mainboard layout and driver
+strength, `t_CASLatency` depend on the supported and configured DRAM CAS
+latency (CL) in CLK cycles, `t_CLKSKEWx` depends on the position of the
+IC on DIMM and reference designed used for the DIMM.
+
+## Read trainining
+
+Read training allows to measure the skew of the DATA/DQS signal,
+compared to the source CLK. It is usually done by firmware.
+As soon as the skew is known, the DATA lanes can be individually delayed
+by a constant rate to synchronize the DATA arriving at the MCH.
+
+For read training the DIMM is placed into a special mode where it outputs
+a known pattern. The pattern looks like this:
+
+![][pat]
+
+[pat]: read_training_pattern.svg
+
+Due to the different skew of the lanes, the data arrives at different times
+on the MCH. It's no longer synchronous to the CLK or other DATA lanes:
+
+![][read1]
+
+[read1]: read_training.svg
+
+The MCH must delay the signals to synchronize them again.
+
+### Delay units
+The MCH is able to delay all lanes individually or at once. The delay
+circuit inside the MCH consists of a *phase delay unit* and *CLK delay units*.
+The *phase delay unit* delays by a fraction of the CLK, while the
+*CLK delay unit* delays in multiple of the CLK.
+
+They can be configured by firmware using registers inside the MCH.
+
+#### Phase delay
+The phase delay unit might look like this:
+
+![][delay64]
+
+[delay64]: 64delay.svg
+
+The phase delay can be adjusted by software by writing a register that selects
+the MUX input. In this example the signal can be shifted by 64 1/64 CLKs.
+
+Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous
+to the CLK as seen by the MCH:
+
+![][read2]
+
+[read2]: read_training2.svg
+
+
+#### CLK delay
+The CLK delay unit might look like this:
+
+![][delay16]
+
+[delay16]: 16delay.svg
+
+The CLK delay can be adjusted by software by writing a register that selects
+the MUX input. In this example the signal can be delayed by 16 CLKs.
+
+Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous
+to the other DQS lanes:
+
+![][read3]
+
+[read3]: read_training3.svg
+
+#### Combined delay
+
+Both units are connected in row for each DQS/DATA lane:
+
+![][blocks]
+
+[blocks]: recv_blocks.svg
+
+For each lane (here 8 + 1), there's a 10bit register allowing to adjust the 
+delay.
+
+## Finding the right delay
+
+Assuming a 1/64th phase delay unit, the firmware guesses the initial skew and then places the phase in the alternating data pattern. It then adjest the phase and measures the sampled value.
+
+The following algorithm is used:
+
+1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern.
+2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low".
+3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern.
+4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge.
+5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge.
+
+Read training has now found the exact delay for each lane and stores the values for the next boot. This feature is known as *Fast Boot* or *MRC cache*.
+
+
+[FlyBy routing]: ddr3_flyby.md
diff --git a/Documentation/getting_started/ram_initialization/recv_blocks.dia b/Documentation/getting_started/ram_initialization/recv_blocks.dia
new file mode 100644
index 0000000..cf554ae
--- /dev/null
+++ b/Documentation/getting_started/ram_initialization/recv_blocks.dia
Binary files differ
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+    <tspan x="314" y="-372">DDR3 Receive delay pseudo implementation</tspan>
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