Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32334
Change subject: Documentation: Explain DDR3 read training ......................................................................
Documentation: Explain DDR3 read training
Add lots of colorful graphics to explain DDR3 read training in detail, what is done inside MCH and what needs to be done on firmware level.
Besides read training give a short explenation what DDR3 "FlyBy" is and compare it with DDR2 DIMMs.
Besides the SVG all sources files are added.
Change-Id: Ib477bd332984c397289404cfc33c65a2d4469257 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/getting_started/index.md A Documentation/getting_started/ram_initialization/16delay.dia A Documentation/getting_started/ram_initialization/16delay.svg A Documentation/getting_started/ram_initialization/64delay.dia A Documentation/getting_started/ram_initialization/64delay.svg A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.dia A Documentation/getting_started/ram_initialization/DRAM_data_clock_lanes_skew.svg A Documentation/getting_started/ram_initialization/ddr3_flyby.md A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia A Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg A Documentation/getting_started/ram_initialization/index.md A Documentation/getting_started/ram_initialization/read_training.dia A Documentation/getting_started/ram_initialization/read_training.svg A Documentation/getting_started/ram_initialization/read_training2.dia A Documentation/getting_started/ram_initialization/read_training2.svg A Documentation/getting_started/ram_initialization/read_training3.dia A Documentation/getting_started/ram_initialization/read_training3.svg A Documentation/getting_started/ram_initialization/read_training_pattern.dia A Documentation/getting_started/ram_initialization/read_training_pattern.svg A Documentation/getting_started/ram_initialization/readtraining.md A Documentation/getting_started/ram_initialization/recv_blocks.dia A Documentation/getting_started/ram_initialization/recv_blocks.svg 22 files changed, 1,989 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32334/1
diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 52d873e..a265c5d 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -7,3 +7,4 @@ * [Gerrit Guidelines](gerrit_guidelines.md) * [Documentation License](license.md) * [Writing Documentation](writing_documentation.md) +* [DDR3 memory initialization](ram_initialization/index.md) diff --git a/Documentation/getting_started/ram_initialization/16delay.dia b/Documentation/getting_started/ram_initialization/16delay.dia new file mode 100644 index 0000000..d0e0095 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/16delay.svg b/Documentation/getting_started/ram_initialization/16delay.svg new file mode 100644 index 0000000..f661ddd --- /dev/null +++ b/Documentation/getting_started/ram_initialization/16delay.svg @@ -0,0 +1,177 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="38cm" height="18cm" viewBox="366 265 754 351" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="367.719" y="266.052" width="751.775" height="348.316"/> + <rect style="fill: none; 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As every DIMM only needs to terminate the line once at end of PCB, +the DC resistance is much lower as on DDR2 "tree" routing topology, which did +terminate on every IC. + +The disadvantage of "fly-by" is the more complex memory training that needs to +be done to find the DATA lane skew. + +After the skew has been measured, the DATA lanes needs to be delayed by the +memory controller, to make sure all signals are still synchronous to the CLK, +as seen be the memory controller (on READ) or the DRAM (on WRITE). + +![][flyby] + +[flyby]: ddr3_vs_ddr2.svg + +```eval_rst ++---------------------------+------------+----------------+ +| Feature | DDR2 | DDR3 | ++===========================+============+================+ +| Frequency | 200-533 | 400-800 | ++---------------------------+------------+----------------+ +| Routing | complex | easy | ++---------------------------+------------+----------------+ +| Termination DC resistance | very high | low | ++---------------------------+------------+----------------+ +| Memory training | easy | complex | ++---------------------------+------------+----------------+ +``` + diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia new file mode 100644 index 0000000..e4b4d09 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.dia Binary files differ diff --git a/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg new file mode 100644 index 0000000..0b8db34 --- /dev/null +++ b/Documentation/getting_started/ram_initialization/ddr3_vs_ddr2.svg @@ -0,0 +1,298 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="17cm" height="10cm" viewBox="507 221 325 192" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="508.366" y="221.748" width="323.85" height="190.069"/> + <rect style="fill: none; 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It is usually done by firmware. +As soon as the skew is known, the DATA lanes can be individually delayed +by a constant rate to synchronize the DATA arriving at the MCH. + +For read training the DIMM is placed into a special mode where it outputs +a known pattern. The pattern looks like this: + +![][pat] + +[pat]: read_training_pattern.svg + +Due to the different skew of the lanes, the data arrives at different times +on the MCH. It's no longer synchronous to the CLK or other DATA lanes: + +![][read1] + +[read1]: read_training.svg + +The MCH must delay the signals to synchronize them again. + +### Delay units +The MCH is able to delay all lanes individually or at once. The delay +circuit inside the MCH consists of a *phase delay unit* and *CLK delay units*. +The *phase delay unit* delays by a fraction of the CLK, while the +*CLK delay unit* delays in multiple of the CLK. + +They can be configured by firmware using registers inside the MCH. + +#### Phase delay +The phase delay unit might look like this: + +![][delay64] + +[delay64]: 64delay.svg + +The phase delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be shifted by 64 1/64 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the CLK as seen by the MCH: + +![][read2] + +[read2]: read_training2.svg + + +#### CLK delay +The CLK delay unit might look like this: + +![][delay16] + +[delay16]: 16delay.svg + +The CLK delay can be adjusted by software by writing a register that selects +the MUX input. In this example the signal can be delayed by 16 CLKs. + +Applied to the DQS as seen on READ command, the signal can be delayed to be synchronous +to the other DQS lanes: + +![][read3] + +[read3]: read_training3.svg + +#### Combined delay + +Both units are connected in row for each DQS/DATA lane: + +![][blocks] + +[blocks]: recv_blocks.svg + +For each lane (here 8 + 1), there's a 10bit register allowing to adjust the +delay. + +## Finding the right delay + +Assuming a 1/64th phase delay unit, the firmware guesses the initial skew and then places the phase in the alternating data pattern. It then adjest the phase and measures the sampled value. + +The following algorithm is used: + +1. Samples all lanes using 128 (64 + 1 full CLK) different phase delays. It allows to find the rising edge in the pattern. +2. In the next step the phase delay is reduced by 32 (1/2 CLK) to position the sample in a logic "low". +3. For each lane the delay is reduced by 128 (2 CLKs) until a logic "high" is sampled. That the preamble of the pattern. +4. As next step the delay is increased by 96 (1.5 CLKs) to position at the first falling edge. +5. Multiple samples in the range -0.5 to 0.5 CLKS are done to find the exact point of falling edge. + +Read training has now found the exact delay for each lane and stores the values for the next boot. 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