[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Update fsp params for Jasper Lake

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38461 )

Change subject: soc/intel/tigerlake: Update fsp params for Jasper Lake
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Patch Set 20:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ch... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ch... 
PS16, Line 208: 	enum {
              : 		DEBUG_INTERFACE_RAM  = 0x1,
              : 		DEBUG_INTERFACE_UART = 0x2,
              : 		DEBUG_INTERFACE_USB3 = 0x4,
              : 		DEBUG_INTERFACE_SERIAL_IO  = 0x8,
              : 		DEBUG_INTERFACE_TRACEHUB = 0x10
              : 	} debug_interface_flag;
> The description does not say about UART. […]

Sorry , my bad, Updated the flags, the dsc description now holds valid too.

https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ro... 
File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/38461/16/src/soc/intel/tigerlake/ro... 
PS16, Line 67: config->PcieClkSrcUsage[i] == 0
> I am still confused. As per tigerlake's chip.h, 0 corresponds to PCH Root port. […]

Agree on this , the Clksrc 0 can be allocated to PCIe RP 0, it is a valid assignment.