2 comments:
File src/soc/intel/tigerlake/chip.h:
enum {
DEBUG_INTERFACE_RAM = 0x1,
DEBUG_INTERFACE_UART = 0x2,
DEBUG_INTERFACE_USB3 = 0x4,
DEBUG_INTERFACE_SERIAL_IO = 0x8,
DEBUG_INTERFACE_TRACEHUB = 0x10
} debug_interface_flag;
The description does not say about UART. […]
Sorry , my bad, Updated the flags, the dsc description now holds valid too.
File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
Patch Set #16, Line 67: config->PcieClkSrcUsage[i] == 0
I am still confused. As per tigerlake's chip.h, 0 corresponds to PCH Root port. […]
Agree on this , the Clksrc 0 can be allocated to PCIe RP 0, it is a valid assignment.
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