[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44014 )

Change subject: src/soc/intel/common/block: Mark only TSEG range as IO_CACHEABLE
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Patch Set 3:

(3 comments)

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@27 
PS3, Line 27: 0x00000000000c0000 - 0x000000007b800000 size 0x7b740000 type 6
Before:

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@50 
PS3, Line 50: 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
            : 0x0000000077000000 - 0x000000007b000000 size 0x04000000 type 0
            : 0x000000007b000000 - 0x000000007b800000 size 0x00800000 type 6
After:

https://review.coreboot.org/c/coreboot/+/44014/3//COMMIT_MSG@58 
PS3, Line 58: MTRR: WB selected as default type.
I don't see any Type 1 MTRRs in here. Could you please share the full bootlog? You can put it on https://paste.flashrom.org (email can be `none`)