Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31525 )
Change subject: mb/ocp/monolake: add TPM and IPMI support ......................................................................
Patch Set 1: Code-Review+1
(3 comments)
https://review.coreboot.org/#/c/31525/1/src/mainboard/ocp/monolake/Kconfig File src/mainboard/ocp/monolake/Kconfig:
https://review.coreboot.org/#/c/31525/1/src/mainboard/ocp/monolake/Kconfig@1... PS1, Line 17: config INTEGRATED_UART Do you have serial output in romstage on cold boot ?
https://review.coreboot.org/#/c/31525/1/src/mainboard/ocp/monolake/romstage.... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/#/c/31525/1/src/mainboard/ocp/monolake/romstage.... PS1, Line 32: 0x0c0ca1); 0x0ca0 is used by the IPMI.
https://review.coreboot.org/#/c/31525/1/src/mainboard/ocp/monolake/romstage.... PS1, Line 33: pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN3_DEC, what are the other entries good for ? Why doesn't it route 6e/6f to LPC ? Does the SuperIO have a different range assigned ?